Broadcom Unveils Cutting-Edge 3.5D XDSiP Technology for Next-Generation AI Accelerators

Broadcom teases 'cutting-edge' 3.5D XDSiP tech: 4 compute tiles, 12 HBM sites fabbed by TSMC

TL;DR: Broadcom has introduced its 3.5D eXtreme Dimension System in Package (XDSiP) technology, enabling AI customers to develop advanced custom accelerators. This platform integrates over 6000 mm² of silicon and up to 12 HBM stacks, enhancing efficiency and reducing power consumption. It combines 3D silicon stacking with 2.5D packaging, offering improved interconnect density, power efficiency, and reduced latency. This innovation addresses the limitations of Moore's Law, Broadcom has just announced its new 3.5D eXtreme Dimension System in Package (XDSiP) platform technology, which enables consumer AI customers to develop next-generation custom accelerators (XPUs). The new 3.55D XDSiP integrates over 6000 mm2 of silicon and up to 12 HBM stacks in a single package, enabling high-efficiency, lower-power computing for AI at scale. Broadcom says that it has achieved this significant milestone by developing and launching the industry's first Face-to-Face (F2F) 3.5D XPU. Broradcom explains: "The immense computational power required for training generative AI models relies on massive clusters of 100,000 growing to 1 million XPUs. These XPUs demand increasingly sophisticated integration of compute, memory, and I/O capabilities to achieve the necessary performance while minimizing power consumption and cost. Traditional methods like Moore's Law and process scaling are struggling to keep up with these demands. Therefore, advanced system-in-package (SiP) integration is becoming crucial for next-generation XPUs". The company continues: "Over the past decade, 2.5D integration, which involves integrating multiple chiplets up to 2500 mm² of silicon and HBM modules up to 8 HBMs on an interposer, has proven valuable for XPU development. However, as new and increasingly complex LLMs are introduced, their training necessitates 3D silicon stacking for better size, power, and cost. Consequently, 3.5D integration, which combines 3D silicon stacking with 2.5D packaging, is poised to become the technology of choice for next-generation XPUs in the coming decade". Key Benefits of Broadcom's 3.5D XDSiP Frank Ostojic, Senior Vice President and General Manager, ASIC Products Division, Broadcom, explains: "Advanced packaging is critical for next generation XPU clusters as we hit the limits of Moore's Law. In close collaboration with our customers, we have created a 3.5D XDSiP platform on top of the technology and tools from TSMC and EDA partners. By stacking chip components vertically, Broadcom's 3.5D platform enables chip designers to pair the right fabrication processes for each component while shrinking the interposer and package size, leading to significant improvements in performance, efficiency, and cost". Dr. Kevin Zhang, Senior Vice President of Business Development & Global Sales and Deputy Co-COO, Taiwan Semiconductor Manufacturing Company, added: "TSMC and Broadcom have collaborated closely over the past several years to bring together TSMC's most advanced logic processes and 3D chip stacking technologies with Broadcom's design expertise. We look forward to productizing this platform to unleash AI innovations and enable future growth".

Broadcom Unveils "Cutting-Edge" 3.5D XDSiP Technology, Embeds Four Compute Tiles & 12 HBM Sites On A Single Package

Broadcom has unveiled its "cutting-edge" 3.5D XDSiP platform technology, focused on custom compute platforms to bring in significant performance and efficiency gains. Broadcom's Newest 3.5D XDSiP Platform Brings In Enablement For Large-Scale AI XPU, Focusing On AI & HPC Workloads [Press Release]: Broadcom Inc. today announced the availability of its 3.5D eXtreme Dimension System in Package (XDSiP) platform technology, enabling consumer AI customers to develop next-generation custom accelerators (XPUs). The 3.5D XDSiP integrates more than 6000 mm² of silicon and up to 12 high bandwidth memory (HBM) stacks in one packaged device to enable high-efficiency, low-power computing for AI at scale. Broadcom has achieved a significant milestone by developing and launching the industry's first Face-to-Face (F2F) 3.5D XPU. The immense computational power required for training generative AI models relies on massive clusters of 100,000 growing to 1 million XPUs. These XPUs demand increasingly sophisticated integration of compute, memory, and I/O capabilities to achieve the necessary performance while minimizing power consumption and cost. Traditional methods like Moore's Law and process scaling are struggling to keep up with these demands. Therefore, advanced system-in-package (SiP) integration is becoming crucial for next-generation XPUs. Over the past decade, 2.5D integration, which involves integrating multiple chiplets up to 2500 mm² of silicon and HBM modules up to 8 HBMs on an interposer, has proven valuable for XPU development. However, as new and increasingly complex LLMs are introduced, their training necessitates 3D silicon stacking for better size, power, and cost. Consequently, 3.5D integration, which combines 3D silicon stacking with 2.5D packaging, is poised to become the technology of choice for next-generation XPUs in the coming decade. Broadcom's 3.5D XDSiP platform achieves significant improvements in interconnect density and power efficiency compared to the Face-to-Back (F2B) approach. This innovative F2F stacking directly connects the top metal layers of the top and bottom dies, which provides a dense and reliable connection with minimal electrical interference and exceptional mechanical strength. Broadcom's 3.5D platform includes IP and proprietary design flow for efficient correct-by-construction of 3D die stacking for power, clock and signal interconnects. Key Benefits of Broadcom's 3.5D XDSiP Broadcom's lead F2F 3.5D XPU integrates four compute dies, one I/O die, and six HBM modules, leveraging TSMC's cutting-edge process nodes and 2.5D CoWoS packaging technologies. Broadcom's proprietary design flow and automation methodology, built upon industry-standard tools, has ensured first-pass success despite the chip's immense complexity. The 3.5D XDSiP has demonstrated complete functionality and exceptional performance across critical IP blocks, including high-speed SerDes, HBM memory interfaces, and die-to-die interconnects. This accomplishment underscores Broadcom's expertise in designing and testing complex 3.5D integrated circuits. TSMC and Broadcom have collaborated closely over the past several years to bring together TSMC's most advanced logic processes and 3D chip stacking technologies with Broadcom's design expertise. We look forward to productizing this platform to unleash AI innovations and enable future growth. - Dr. Kevin Zhang, SvP of Business Development & Global Sales and Deputy Co-COO, TSMC With more than five 3.5D products in development, a majority of Broadcom's consumer AI customers have adopted the 3.5D XDSiP platform technology with production shipments starting February 2026. For more information on Broadcom's 3.5D custom compute platform, please click here.