Rambus Unveils HBM4 Memory: A Leap in High-Bandwidth Computing

Rambus Outlines HBM4 Memory Controller: Up To 10 Gb/s Speeds, 2.56 TB/s Bandwidth & 64 GB Capacities Per Stack

Rambus has detailed its next-gen HBM4 Memory Controller which will allow significant uplifts over existing HBM3 and HBM3E solutions. HBM4 Will Begin the next chapter of AI & Data Center Evolution, Delivering Faster Memory Speeds & Higher Capacities Per Stack As JEDEC moves towards the finalization of the HBM4 memory spec, we have our first details of what the next-generation solution would offer. Aimed primarily at the AI and Data Center market, the HBM4 memory solution is going to continue to expand the capabilities of existing HBM DRAM design. Starting with the details, Rambus announced its HBM4 memory controller which is going to offer over 6.4 Gb/s speeds per pin which should be faster than the first generation of HBM3 solution while offering more bandwidth than HBM3E solutions using the same 16-Hi stack and 64 GB max capacity design. The starting bandwidth for HBM4 is rated at 1638 GB/s which is 33% higher than HBM3E and 2x higher than HBM3. Currently, HBM3E solutions operate at up to 9.6 Gb/s speeds with up to 1.229 TB/s of bandwidth per stack. With HBM4, the memory solution is going to offer up to 10 Gb/s speeds and up to 2.56 GB/s of bandwidth per HBM interface. That will mark more than a 2x increase over HBM3E but the full capabilities of HBM4 memory won't be seen for a while and only become accessible once yields get better. Other features of the HBM4 memory solution include ECC, RMW (Read-Modify-Write), Error Scrubbing, etc. As of right now, SK Hynix has reportedly begun mass production of its 12-layer HBM3E memory with up to 36 GB capacities and 9.6 Gbps speeds while its next-gen HBM4 memory is expected to tape out this month. Meanwhile, Samsung is expected to go into mass production for its HBM4 memory by the end of 2025 with tape out expected this quarter. As of right now, NVIDIA's Rubin GPUs which are expected to arrive in 2026 are going to be the first AI platform to feature HBM4 memory support while Instinct MI400 is also expected to utilize the next-gen design however AMD hasn't confirmed that yet.

Rambus details HBM4 memory controller: up to 10Gb/s, 2.56TB/sec bandwidth, 64GB per stack

Rambus has provided more details on its upcoming HBM4 memory controller, which offers some huge upgrades over current HBM3 and HBM3 memory controllers. JEDEC is still finalizing the HBM4 memory specifications, with Rambus teasing its next-gen HBM4 memory controller that will be prepared for next-gen AI and data center markets, continuing to expand the capabilities of existing HBM DRAM designs. Rambus' new HBM4 controller will pump over 6.4Gb/s speeds per pin, which is faster than the first-gen HBM3 and has more bandwidth than faster HBM3E memory using the same 16-Hi stack and 64GB max capacity design. HBM4 starting bandwidth is at 1638GB/sec (1.63TB/sec) which is 33% faster than HBM3E and 2x faster than HBM3. HBM3E memory operates at 9.6Gb/s speeds with up to 1.229TB/sec of memory bandwidth per stack, while HBM4 memory will offer up to 10Gb/s speeds and a much bigger 2.56TB/sec of bandwidth per HBM interface. This is a 2x increase over the just-launched HBM3E, but the full capabilities of HBM4 memory won't be realized for a while yet (NVIDIA's next-gen Rubin R100 will use HBM4 in 2026). Rambus talked about some of the other features of HBM4, which include ECC, RMW (Read-Modify-Write), Error Scrubbing, and more. South Korean memory giant SK hynix is the only company mass-producing new 12-layer HBM3E memory with up to 36GB capacities and 9.6Gbps speeds, but next-gen HBM4 memory from SK hynix is expected to tape out next month, while Samsung is gearing into HBM4 mass production before the end of 2025, with tape out expected in Q4 2024. We're expecting the next-gen NVIDIA Rubin R100 AI GPUs to use a 4x reticle design (compared to Blackwell with 3.3x reticle design) and made on TSMC's bleeding-edge CoWoS-L packaging technology on the new N3 process node. TSMC recently talked about up to 5.5x reticle size chips arriving in 2026, featuring a 100 x 100mm substrate that would handle 12 HBM sites, versus 8 HBM sites on current-gen 80 x 80mm packages. TSMC will be shifting to a new SoIC design that will allow larger than 8x reticle size on a bigger 120 x 120mm package configuration, but as Wccftech points out, these are still being planned, so we can probably expect somewhere around the 4x reticle size for Rubin R100 AI GPUs.