Intel Unveils Ambitious Clearwater Forest CPUs: 288 E-Cores and Advanced 18A Process

Intel Clearwater Forest CPUs to Feature 288 E-Cores on Intel 18A

Intel is preparing its next big step in server CPUs with the Clearwater Forest family, and the details shared at the Hot Chips conference give a clear look at how ambitious this project is. These chips are designed entirely around efficiency-focused cores, known as E-cores, and the flagship versions will pack as many as 288 cores per processor. That's double the maximum core count offered in today's Sierra Forest lineup. Clearwater Forest is built on the Intel 18A process node, which is part of Intel's latest manufacturing roadmap and brings with it a big shift in transistor design. Instead of the older FinFET structures, 18A uses gate-all-around transistors, which offer better control of current flow and lower leakage, making them more efficient at scale. On top of this, Intel is adding an option for backside power delivery, a way of routing power through the rear of the wafer that can improve stability and energy use in very dense chips. At the heart of Clearwater Forest lies the Darkmont architecture, Intel's latest iteration of its E-core design. These cores are not focused on per-core performance like the company's P-cores, but instead aim to deliver massive throughput when combined in large numbers. Still, Intel claims Darkmont brings meaningful per-core gains: a 17% boost in IPC compared to the previous E-core generation. Some of this comes from a stronger front-end, which is the part of the CPU pipeline that fetches and prepares instructions, and a more capable out-of-order engine, which allows the processor to juggle more instructions at once. Caching has also been upgraded. Every four cores share 4 MB of L2 cache running at a 400 GB/s bandwidth, which is double the bandwidth seen in Sierra Forest. The physical layout of these CPUs is also changing. Rather than building a huge monolithic die, Intel is taking a chiplet approach. Each Clearwater Forest CPU can be composed of up to twelve compute tiles, and each of those tiles houses 24 Darkmont E-cores. This means the top model reaches that 288-core mark by stacking together many smaller units. These compute tiles are built on Intel 18A, but they sit on top of three base dies manufactured with Intel 3 technology. The base dies handle 576 MB of last-level cache (LLC) and provide the connection to DDR5-8000 memory controllers. To round out the design, there are also two I/O chiplets produced on Intel 7, which manage external connections such as PCIe. Memory and scaling capabilities are where Clearwater Forest really shows its data center focus. Each CPU supports twelve DDR5-8000 channels, offering up to 1.3 TB/s of memory bandwidth. When two of these processors are installed on a dual-socket motherboard, a system can reach 576 E-cores in total, paired with up to 3 TB of system RAM and more than 1 GB of shared LLC. This kind of density is clearly aimed at hyperscale cloud providers, AI inference workloads, and large-scale data handling tasks, where packing as many cores and as much memory bandwidth as possible into a server rack is critical. Intel has not provided a firm release date, but Clearwater Forest is targeted for 2026 availability. By then, the competitive landscape will also include high-core-count AMD EPYC chips and various ARM-based server processors that emphasize energy efficiency and scaling. Intel's bet is that the combination of its 18A process, Darkmont architecture, and a highly modular chiplet design will keep it competitive in that environment. For customers, the key takeaway is that Clearwater Forest is all about core density, memory bandwidth, and efficiency rather than chasing maximum single-thread performance. It represents Intel's strategy to regain ground in the data center market by focusing on what hyperscalers and large cloud operators actually need: lots of cores, fast memory access, and power-efficient scaling. Feature Sierra Forest Clearwater Forest Max Cores per CPU Up to 144 E-cores Up to 288 E-cores Core Architecture Crestmont E-cores Darkmont E-cores Process Node (Compute Tiles) Intel 3 Intel 18A (1.8nm-class) Cache per 4 Cores (L2) 4 MB (200 GB/s) 4 MB (400 GB/s) Last-Level Cache (LLC) Up to 480 MB 576 MB Memory Support 12-channel DDR5-6400 12-channel DDR5-8000 Memory Bandwidth per CPU ~1.0 TB/s 1.3 TB/s Socket Scaling Dual-socket (288 cores) Dual-socket (576 cores)

Intel's Next-Gen Clearwater Forest "E-Core" Xeon CPU Unveiled: 12 CPU Chiplets On 18A Node, 288 Darkmont Cores, 17% IPC Increase, 2x L2 Cache Bandwidth, DDR5-8000 Support

Intel has just unveiled new information on its next-gen Clearwater Forest "E-Core" Xeon CPUs with up to 288 cores, based on the 18A process node. Intel's next-gen E-Core only "Xeon" family, codenamed Clearwater Forest, is making its way to servers soon. Just like how the Xeon 6 lineup was segmented into P-Core and E-Core flavors, such as Granite Rapids & Sierra Forest, we will see the next-gen Xeon family in P-Core only "Diamond Rapids" & E-Core only "Clear Water Forest" lineups. The P-Core family is optimized for performance & tackles more compute-intensive and AI workloads, while the E-Core only family is optimized for efficiency & tackles high-density / scale-out workloads. In its Hot Chips 2025 presentation, Intel outlined that Clearwater Forest Xeon CPUs will be fabricated on the company's latest and greatest 18A process node, which is also being used by Panther Lake on the client side, arriving later this year. Some of the main highlights of the new Xeon E-Core CPU include: Starting with the process technology, Intel's Clearwater Forest is based on the aforementioned 18A node and utilizes Backside metal combined with gate-all-around to provide numerous benefits beyond just FET Z scaling. 18A brings lowered gate capacitance, which improves core logic power efficiency, higher cell density with over 90% cell utilization rates, improved signal routing, which helps reduce RC delay and further improves efficiency, and lastly, offers low-loss power delivery with losses being reduced by 4-5%. Coming to the architecture, Intel is leveraging its Darkmont E-Core design for Clearwater Forest, which is an update to Sierra Glen E-Cores used by Sierra Forest. These cores offer: The front end features a 64kB Instruction cache, three 3-Wide instruction decoders that offer 50% more instruction bandwidth with nine decodes per cycle, and a much more accurate branch predictor, possibly using deep branch history and larger structure sizes. The OOE (Out-of-Order Engine) sees an upgrade too, with 8-wide allocation (60% increase), with 16-wide retire (2x increase) for execution parallelism. The entry out-of-order window size is increased by 60% with 416 units, while 26 execution ports offer a 50% increase versus the prior generation. The Execution Engine sees 26 execution ports to address a range of workloads, while dedicated hardware offers improved efficiency. The Integer and Vector Execution units are increased by 2x while Load Address Generation sees a 1.5x increase, and 2x uplift for Store Address Generation. The core memory subsystem gets a 50% increase to Three-Load while the Two Store remains the same. The issuing of loads earlier could help reduce latency. Deep Buffering supports up to 128 outstanding L2 misses (2x increase). There are also advanced prefetchers on Clearwater Forest, while the list of Xeon E-Core specific features includes: Intel is also leveraging a new modular architecture with Clearwater Forest "E-Core" Xeon CPUs. This includes 4 MB of Unified L2 cache with 17 latency cycles per four-core cluster for up to 288 MB of L2. The L2 cache also offers much higher bandwidth with up to 2x increase or 400 GB/s. The IPC increase is rated at 17% as per measurements conducted in SpecIntRate'17. Each core shares 200 GB/s of bandwidth with the L2 cache, while a 35 GB/s fabric interconnect connects the clusters together. Intel went all 3D when building Clearwater Forest, with a total of 12 CPU chiplets, which are fabricated on the 18A process node. These sit on three individual base tiles, which include the Fabric, LLC, memory controllers, and IO, & are based on Intel 3 process node. The interposer houses two I/O chiplets based on Intel 7 and features high-speed IO, fabric, and accelerators. The communication is handled by Intel's EMIB interconnect solution. So in total: Clearwater Forest also uses a monolithic mesh coherent fabric, which uses shorter routes, more metal resources, and a high-density interconnect for improved power efficiency. In the end, Intel shares some performance aspects of a 2S Clearwater E-Core Xeon solution. The CPUs support 12-channel DDR5-8000 memory with up to 3 TB capacities in a dual-socket server, and up to 1300 GB/s of memory bandwidth. The platform supports 2 x 96 PCIe Gen5 and 64 CXL lanes, 144 UPI (576 GB/s), and with a 576 core + 1152 MB LLC solution, you reach up to 59 TF/s that packs 5000 GB/s of raw bandwidth.