Stanford team builds first commercial 3D chip at US foundry with 4x AI performance gains

First truly 3D chip fabbed at US foundry, features carbon nanotube transistors and RAM on a single die -- future devices could have up to 1000x improvement in energy-delay product

Prototype manufactured at SkyWater shows dense vertical memory-logic integration with measured and simulated AI speedups. A collaborative research team has demonstrated what it says is the first monolithic 3D integrated circuit manufactured at a commercial U.S. foundry, reporting substantial performance gains over conventional flat chip designs. The prototype was developed by engineers from Stanford, Carnegie Mellon, the University of Pennsylvania, and MIT, and fabricated in partnership with SkyWater Technology. The chip departs from conventional two-dimensional layouts by stacking memory and logic directly on top of one another in a single, continuous process. Instead of assembling multiple finished dies into a package, the researchers built each device layer sequentially on the same wafer using a low-temperature process designed not to damage underlying circuitry, resulting in a dense network of vertical interconnects that shortens data paths between memory cells and compute units. The prototype was manufactured on SkyWater's 200mm production line, using a mature 90nm to 130nm process. The stack integrates conventional silicon CMOS logic with resistive RAM layers and carbon nanotube field-effect transistors, all fabricated under a thermal budget of about 415°C. According to the team, early hardware tests show roughly a four-fold improvement in throughput compared with a comparable 2D implementation operating at similar latency and footprint. Beyond the measured hardware results, the researchers also evaluated taller stacks through simulation. Designs with additional tiers of memory and compute showed up to a twelve-fold performance improvement on AI-style workloads, including models derived from Meta's LLaMA architecture. The group further argues that the architecture could eventually deliver 100-fold to 1,000-fold improvements in energy-delay product, a combined metric of speed and efficiency, by continuing to scale vertical integration rather than shrinking transistors. While academic labs have previously demonstrated experimental 3D chips, the team emphasizes that this work differs in being built in a commercial foundry environment rather than a bespoke research line. SkyWater executives involved in the project described the effort as proof that monolithic 3D architectures can be transferred into domestic manufacturing flows, rather than remaining confined to university cleanrooms. "Turning a cutting-edge academic concept into something a commercial fab can build is an enormous challenge," said co-author Mark Nelson, vice president of technology development operations at SkyWater Technology. The team presented their research at the IEEE International Electron Devices Meeting (IEDM 2025) between December 6 and 10.

US engineers develop 3D chip that offers order-of-magnitude speed gains

Engineers in the United States have developed a novel multilayer computer chip with a unique architecture that could help usher in a new era of AI hardware and domestic semiconductor innovation. The team highlighted that in hardware tests and simulations, the new 3D chip outperforms 2D chips by roughly an order of magnitude. Unlike today's largely flat, 2D chips, the new prototype's key ultra-thin components rise like stories in a tall building, with vertical wiring acting like numerous high-speed elevators that enable fast, massive data movement. Its record-setting density of vertical connections and carefully interwoven mix of memory and computing units help the chip bypass the bottlenecks that have long slowed improvement in flat designs. "This opens the door to a new era of chip production and innovation," said Subhasish Mitra, the William E. Ayer Professor in Electrical Engineering and professor of computer science at Stanford University, and principal investigator of a new paper describing the chip presented at the 71st Annual IEEE International Electron Devices Meeting (IEDM). "Breakthroughs like this are how we get to the 1,000-fold hardware performance improvements future AI systems will demand." While academic labs have previously built experimental 3D chips, this is the first time such a chip has shown clear performance gains and been manufactured in a commercial foundry. The team also pointed out that on conventional 2D chips, components sit on a single, flat surface with limited, spread-out memory, so data must travel across a few long, crowded routes. Because the computing elements run much faster than the data can move - and because the chip can't store enough memory close by - the system ends up constantly waiting on information. Engineers call this bottleneck the "memory wall," the point at which processing speed outpaces the chip's ability to deliver data, according to a press release. "By integrating memory and computation vertically, we can move a lot more information much quicker, just as the elevator banks in a high-rise let many residents travel between floors at once," said Tathagata Srimani, assistant professor of electrical and computer engineering at Carnegie Mellon University, the paper's senior author, who began the work as a postdoctoral fellow advised by Mitra.