Intel Unveils Ambitious Clearwater Forest CPUs: 288 E-Cores and Advanced 18A Process

Intel's Ambitious Clearwater Forest CPU Architecture

Intel has unveiled its next-generation server CPU architecture, Clearwater Forest, at the Hot Chips conference, showcasing a significant leap in efficiency-focused computing 1

1

2

2

. This new family of processors is designed to address the growing demands of hyperscale cloud providers, AI inference workloads, and large-scale data handling tasks.

Core Architecture and Performance Improvements

At the heart of Clearwater Forest lies the Darkmont architecture, Intel's latest iteration of its E-core (efficiency core) design. These CPUs are built entirely around E-cores, with the flagship versions featuring an impressive 288 cores per processor – double the maximum core count offered in the current Sierra Forest lineup 1

1

.

Intel claims that Darkmont brings meaningful per-core gains:

• 17% boost in Instructions Per Cycle (IPC) compared to the previous E-core generation
• Stronger front-end for improved instruction fetching and preparation
• More capable out-of-order engine, allowing the processor to juggle more instructions simultaneously
• Upgraded caching system with 4 MB of L2 cache shared between every four cores, running at a 400 GB/s bandwidth – double that of Sierra Forest 1

  1

  2

  2

Advanced Manufacturing Process: Intel 18A

Clearwater Forest is built on the Intel 18A process node, representing a significant advancement in the company's manufacturing capabilities 1

1

2

2

. Key features of this process include:

• Gate-all-around transistors, replacing older FinFET structures
• Better control of current flow and lower leakage, improving efficiency at scale
• Option for backside power delivery, enhancing stability and energy use in dense chip designs 1

  1

Innovative Chiplet Design

Intel has adopted a modular approach for Clearwater Forest, moving away from a monolithic die design:

• Up to twelve compute tiles, each housing 24 Darkmont E-cores
• Compute tiles built on Intel 18A process
• Three base dies manufactured with Intel 3 technology, handling 576 MB of last-level cache (LLC) and DDR5-8000 memory controller connections
• Two I/O chiplets produced on Intel 7, managing external connections such as PCIe 1

  1

  2

  2

Memory and Scaling Capabilities

Clearwater Forest demonstrates its data center focus through impressive memory and scaling features:

• Support for twelve DDR5-8000 channels per CPU
• Up to 1.3 TB/s of memory bandwidth per processor
• Dual-socket configurations can reach 576 E-cores in total
• Support for up to 3 TB of system RAM and more than 1 GB of shared LLC in dual-socket setups 1

  1

  2

  2

Market Positioning and Availability

Intel is targeting a 2026 release for Clearwater Forest, positioning it to compete with high-core-count AMD EPYC chips and ARM-based server processors 1

1

. The focus on core density, memory bandwidth, and efficiency rather than maximum single-thread performance reflects Intel's strategy to regain ground in the data center market by catering to the specific needs of hyperscalers and large cloud operators.

Comparison with Previous Generation

| Feature | Sierra Forest | Clearwater Forest | |---------|---------------|-------------------| | Max Cores per CPU | Up to 144 E-cores | Up to 288 E-cores | | Core Architecture | Crestmont E-cores | Darkmont E-cores | | Process Node (Compute Tiles) | Intel 3 | Intel 18A (1.8nm-class) | | Cache per 4 Cores (L2) | 4 MB (200 GB/s) | 4 MB (400 GB/s) | | Last-Level Cache (LLC) | Up to 480 MB | 576 MB | | Memory Support | 12-channel DDR5-6400 | 12-channel DDR5-8000 | | Memory Bandwidth per CPU | ~1.0 TB/s | 1.3 TB/s | | Socket Scaling | Dual-socket (288 cores) | Dual-socket (576 cores) |

1

1

2

2