Rapidus unveils glass interposer tech to challenge TSMC's dominance in AI chips production

Rapidus Introduces Glass Interposer to Reduce Production Costs

Rapidus, Japan's state-backed chipmaker, has unveiled a prototype glass interposer that marks a significant shift in how AI chips are manufactured. The technology, which the company claims is the world's first to be cut from a large square glass substrate rather than a conventional silicon wafer, could lower production costs substantially and strengthen Japan's position against industry leader TSMC1

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. The company plans to begin mass production in 2028, integrating the glass interposer into its roadmap for next-generation AI processors designed to handle increasingly demanding AI workloads1

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The innovation centers on chip packaging, where interposers serve as critical components connecting multiple chips within a single package. Traditional interposers are produced from 300-millimeter silicon wafers, but Rapidus uses a 600-millimeter-by-600-millimeter glass substrate instead. This format significantly reduces material waste and boosts output, with a single glass substrate yielding more than ten times as many interposers as traditional methods1

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. The larger format also enables production of interposers about 1.3 to 2 times bigger than rivals', allowing more chips to be integrated into one package while offering higher power efficiency than silicon—an increasingly important factor for energy-intensive AI applications.

Japan's Semiconductor Industry Leverages Display Manufacturing Expertise

To overcome technical challenges including fragility during handling and warping risk as substrate sizes increase, Rapidus recruited former engineers from Japanese display makers such as Sharp1

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. The company began pilot production in June 2025 at a cleanroom facility in Chitose, Hokkaido. By adapting mature liquid crystal display glass processing techniques for semiconductor use, Rapidus has significantly lowered development barriers—a 600-millimeter substrate is large by semiconductor standards but relatively small in the LCD panel industry1

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Rapidus senior managing executive officer Yasumitsu Orii emphasized that the company's lack of legacy manufacturing constraints allows it to adopt materials best suited for AI chips without being tied to existing processes1

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. This strategic advantage could prove crucial as the company works to challenge industry leaders in the advanced semiconductors market.

AI-Enhanced Design Tools Target Cost and Time Savings

Beyond manufacturing innovations, Rapidus announced a suite of AI-enhanced design tools at SEMICON Japan 2025, including Raads Generator, an AI-assisted design tool modeled on large-scale language models and optimized for 2-nanometer chips manufacturing2

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. The company has estimated that AI integration will enable it to halve the length of design time and cut design costs by 30%2

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Takashi Ikuno, an associate professor at Tokyo University of Science, noted that AI will be "critical" for Japan's semiconductor industry, stating that "Japan can't realistically compete with leading foundries such as TSMC from the viewpoint of scale and accumulated manufacturing experience. AI offers a way to compensate for these disadvantages by accelerating design cycles and reducing development costs"2

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. Major players including Nvidia, Intel, and Samsung have already adopted AI "digital twins" to boost design productivity2

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Ambitious Roadmap Backed by Government Funding

Rapidus plans to release a process design kit for 2-nanometer chips around March 2026 and aims to begin full-scale production in the second half of fiscal year 2027, which runs from April 2027 to March 20281

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. According to a business plan submitted to the Ministry of Economy, Trade and Industry, Rapidus targets mass production of 1.4-nanometer chips in fiscal years 2029 to 20301

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Total investment for developing and producing 2nm chips is projected to reach approximately JPY4 trillion (US$25.8 billion), while investments for the 1.4nm technology and subsequent generations are expected to surpass JPY3 trillion1

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. The Japanese government has committed cumulative support of about JPY2.9 trillion through fiscal year 2027 and plans to invest an additional JPY100 billion in fiscal year 2025 through the Information-technology Promotion Agency1

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. On the private side, Rapidus aims to raise about JPY130 billion in fiscal year 2025 and reach a cumulative total of JPY1 trillion by fiscal year 2031, with Honda, Fujitsu, and Canon among the companies that could join Toyota Motor and other existing shareholders as new investors1

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Global Competition Intensifies at 2-Nanometer Node

While Rapidus advances its technology, TSMC continues to reinforce its leadership in 2-nanometer technology by expanding manufacturing sites and improving power efficiency and performance tailored for AI workloads3

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. The Taiwan-based foundry is pairing the advanced node with its Chip-on-Wafer-on-Substrate packaging technology to support larger and more complex computing demands3

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. Demand for cutting-edge capacity is tightening, with Apple and Nvidia securing much of TSMC's most advanced 2-nanometer output3

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Major chipmakers are also exploring alternatives to silicon wafer substrates. Intel is developing its own glass substrate technology, while Samsung is working to stabilize yields and scale production at its fabrication plants in the U.S. and South Korea1

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. A January 2025 report indicated that Rapidus is preparing to deliver 2-nanometer chip samples to Broadcom, leveraging IBM-backed technology and heavy government funding to build a homegrown advanced chip manufacturing base3

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