IBM Unveils Dual-Architecture Chip Running Arm and Z Instructions at 5.7 GHz on 2nm Process
9 Sources
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IBM's first dual-ISA core natively executes ARM and z/Architecture in the same core; all cores run at 5.7 GHz base frequency -- next-gen mainframe AI processor is built on 2nm node with 11 cores
IBM's next-gen AI processor is the first time it has supported dual ISA execution natively within the same core. Born out of a collaboration between IBM and Arm that was announced in April, the chip is designed to bring the software support available across the Arm ecosystem to IBM's mainframes,
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IBM announces chip that natively executes Arm and Z instructions concurrently
IBM has revealed it is working on a chip with processor cores that can execute instructions for its own mainframe chips and for the Arm architecture - and for the LinuxONE architecture too for good measure. Big Blue says the unnamed chip will be built on a two-nanometer technology node, include 11
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IBM is building a dual-architecture mainframe chip that will run Arm and Z software on the same cores
Serving tech enthusiasts for over 25 years. TechSpot means tech analysis and advice you can trust. First look: IBM is developing a mainframe chip designed to run Arm software directly alongside IBM Z and LinuxONE code. The approach could let customers add Linux, cloud and AI applications while
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IBM unveils 2nm processor built for dual-architecture computing
IBM has unveiled a 2-nanometer processor designed to bring Arm computing directly into its mainframe systems, allowing enterprises to run Arm-native Linux alongside existing IBM workloads. Announced at the Hot Chips conference, the processor is the first dual-architecture mainframe chip from IBM
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IBM's next-gen mainframe chip is the first to run Arm and Z workloads on the same cores
IBM is announcing today at the annual Hot Chips conference what may be the most consequential change to mainframe architecture in decades: a processor whose cores can natively execute both IBM's own instruction set and Arm's -- switching between the two in nanoseconds. The chip, which will power
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Two architectures on one chip: Arm and IBM team up in a legendary crossover, but alas it's for 'enterprise infrastructure'
Though us PC gamers are unlikely to get the benefit of it, sometimes some new bit of PC hardware comes out of the enterprise market that just makes you go 'huh, that's neat'. Today, it's a new chip from IBM made in collaboration with Arm that runs architectures from both companies on a single chip.
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IBM is developing a dual-architecture chip to run Arm-native AI apps on Z mainframes and Linux servers
IBM is developing a dual-architecture chip to run Arm-native AI apps on Z mainframes and Linux servers IBM Corp. said today at the annual Hot Chips 2026 conference that it's developing a groundbreaking new dual-architecture processor in partnership with the British chip design firm Arm Holdings
[8]
IBM takes another giant step in the AI race
IBM (IBM) unveiled the first mainframe processor built to run two rival computing architectures on a single core, disclosing the design at the Hot Chips conference on Monday, August 24, according to a press release. Any enterprise architect who has ever been told a piece of software will not run
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IBM Announces First Dual-Architecture Mainframe Processor for IBM Z and Linuxone
IBM announced the first dual-architecture mainframe processor, which is being designed to enable enterprises to run operating systems and applications on both the IBM and Arm compute platforms in future IBM Z and LinuxONE systems. The new processor is being developed to allow organizations to run
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IBM revealed its first dual-architecture chip at Hot Chips 2026, featuring 11 cores built on 2nm process running at 5.7 GHz base frequency. Each core natively executes both Arm and Z instructions, switching between architectures in nanoseconds. The processor brings Arm's 22 million-developer ecosystem to mainframes while maintaining mission-critical reliability for enterprises.
IBM Breaks New Ground with Dual-ISA Mainframe Processor
IBM announced its first dual-architecture chip at the Hot Chips conference, marking what may be the most significant shift in mainframe architecture in decades
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. The next-gen mainframe AI processor features 11 high-performance cores built on a 2-nanometer process, each capable of natively executing both z/Architecture and AArch64 instructions at a base frequency above 5.7 GHz1
. The chip represents the first hardware milestone from IBM's collaboration with Arm, announced in April, and is designed to power future IBM Z and LinuxONE systems expected to arrive in 20282
.What sets this processor apart is IBM's engineering approach. Rather than creating a heterogeneous chip with separate Arm cores packaged alongside Z cores, IBM built each core to be bilingual. "Each processor core can natively execute Arm and IBM Z, or Arm and LinuxONE, instructions concurrently," IBM stated
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. The cores can switch between instruction sets dynamically within nanoseconds, with IBM claiming this switching overhead "amortizes to zero" in terms of performance impact5
. During the Hot Chips 2026 reveal, IBM stated it believes this is the first processor to treat both ISAs as "first-class citizens"1
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Source: Tom's Hardware
Technical Architecture Enables Seamless ISA Switching
The dual-architecture chip relies on the Linux Kernel-level Virtual Machine (KVM hypervisor) to support AArch64 instructions, the same mechanism that allows IBM to support Linux on Z mainframes
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. Standard z/Architecture instructions bypass KVM entirely. Enterprises can run Arm64 Linux virtual machines and Linux on Z virtual machines side by side, with the hypervisor dispatching each virtual machine onto a physical core that flips into the corresponding mode5
.The chip includes a full hardware implementation of AArch64 v9.3 with Scalable Vector Extension (SVE) support, handling 2,792 AArch64 instructions
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. IBM built automation tools to consume the ARM XML specifications and understand how to move instructions through the core, with the decode stage representing the biggest area of silicon expansion to support decoding AArch64 instructions1
. The core supports simultaneous multithreading, available to both ISAs, and implements new hardware structures for SVE and special data types like FP161
.Performance Specifications and Memory Architecture
The 2nm processor represents a substantial upgrade over IBM's current Telum II processor introduced in 2024, which features eight cores operating at up to 5.5 GHz
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. The new chip comes with 36 MB of private L2 cache, 432 MB of virtual L3 cache, and as much as 3.5 GB of virtual L4 cache—resources intended to keep latency low for large databases and transaction-heavy workloads3
. Christian Jacobi, Chief Technology Officer and IBM Fellow at IBM Systems Development, emphasized the performance: "That's really, really fast compared to what you otherwise get in the industry. It's just another example of how mainframe technology is not old technology. It's very modern, leading-edge technology"5
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Source: The Register
The processor includes AI inference accelerators for in-transaction fraud detection, a dedicated on-chip data processing unit for I/O acceleration, and hardware accelerators for compression, cryptography, and sorting
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. IBM also revealed its next-generation Spyre AI accelerator at Hot Chips 2026, featuring 16 cores with optimizations for newer AI data formats including FP4/MXFP41
. The new accelerator transitions from LPDDR5 to HBM3e memory, with each accelerator containing 96 GB of HBM3e offering up to 4TB/s bandwidth—20x that of LPDDR51
.Related Stories
Strategic Shift Addresses Software Ecosystem Gap
The dual-architecture chip tackles a fundamental challenge facing IBM's mainframe business: the growing divergence between where enterprise software development happens and where mission-critical workloads run. Meredith Stowell, IBM's vice president for the zSystems Ecosystem, noted that "The Arm ecosystem includes more than 22 million developers worldwide and supports a rapidly growing portfolio of cloud-native, AI, analytics, infrastructure, and enterprise applications"
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. Much of the development in the software world, particularly around AI frameworks like PyTorch and ONNX Runtime, happens with x86 and Arm targets in mind, leaving the mainframe to figure out its own solution1
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Source: VentureBeat
Tina Tarquinio, chief product officer at IBM for IBM Z and LinuxONE, explained the strategic imperative: "No matter how great our ecosystem team is, we would never be able to work with all of them and port them all"
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. IBM's dual-ISA core can execute Arm software without modifications, allowing Arm-based virtual machines to run as if they were operating on native-Arm silicon1
. This approach allows businesses to unify deployment rather than relying on separate Arm or x86 servers and z/Architecture mainframes for different purposes1
.Market Implications and Future Outlook
George Cozma, an analyst at TechInsights, characterized the chip as "ending the platform's historical isolation from the broader computing mainstream," noting that while IBM Z's core strengths of reliability, security, and virtualization "remain the gold standard for mission-critical operations, they are tethered to an architecture that has increasingly diverged from the modern software development lifecycle"
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. The mainframe market remains "small in unit terms" but "strategically important," with customers rarely replacing these systems because "core applications, decades of operational practice, and data gravity make migration expensive and risky"3
.IBM says its Z and LinuxONE systems run 68% of the world's production IT workloads, while 77 of the world's 100 largest banks use the platforms
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. The chip is a likely candidate for the z18 mainframe family, as IBM released its most recent generation, the z17, in 2025 and typically delivers new models every three years2
. Watch for how enterprises in highly regulated industries adopt this technology to run cloud-native and AI workloads alongside core transaction processing, and whether the approach successfully bridges the gap between mainframe reliability and modern software ecosystems.References
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