Samsung unveils HBM5 with Heat Path Block cooling as thermal race with SK hynix intensifies

Samsung HBM5 debuts with Heat Path Block thermal innovation

Samsung Electronics unveiled its first physical mockup of Samsung HBM5 at Computex 2026 in Taipei, showcasing a new in-package cooling structure called Heat Path Block (HPB) that addresses mounting thermal challenges in next generation memory chips 1

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. The timing signals an escalating competition in thermal management, as rival SK hynix unveiled its own SK hynix iHBM cooling design just last week, meaning both Korean memory giants are now targeting the same die-to-die hotspot in the interface connecting memory to processors 1

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The Heat Path Block technology employs a chimney-like structure that builds separate thermal pillars to extract heat from inside the stack and carry it to a spreader positioned above or beside the package 3

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. Rather than allowing heat to escape outward through the core dies, HPB creates a dedicated thermal dissipation pathway that sits beside the Core Die on the same Base Die, connected via D2D PHY 2

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. Samsung stated this method enables heat dissipation without adding complexity to the IC design of high-bandwidth memory core dies or the stacked HBM cube layout 3

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Advanced manufacturing with 2nm base die production

Samsung confirmed it will fabricate the HBM5 memory technology base die using its in-house 2nm base die process, a significant step down from the 4nm node used for HBM4 and HBM4E 1

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. The company plans to utilize Samsung Foundry's GAA nodes to improve power efficiency and performance 3

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. For HBM core dies, Samsung will deploy a 1cnm front-end process and partially implement hybrid bonding technology 3

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Citi analysts noted that Samsung Electronics is expected to significantly enhance thermal stability by adopting HPB technology, which has already been used for Samsung's mobile SoC, Exynos 2600 3

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. The dual capability of running both a memory business and a logic foundry allows Samsung to build the HBM5 stack and the 2nm die beneath it entirely in-house, creating synergy between its memory and foundry operations 1

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Why thermal management matters for AI datacenters

The focus on in-package cooling designs reflects a critical bottleneck in the D2D PHY layer, the high-speed link between the HBM base die and GPU, where power density and temperatures increase exponentially as stacks grow taller and run faster 1

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. Samsung has already implemented and verified HPB on HBM4E, whose first 12-layer samples it began shipping last month at 14 Gbps, scaling to 16 Gbps, with 3.6 TB/s of bandwidth per stack 1

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A roadmap from KAIST projected HBM5 reaching a 4,096-bit interface, roughly 4 TB/s per stack, and about 100 watts of per-stack power—a thermal load explaining why both Korean memory giants are reworking their packaging now rather than at launch 1

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. "AI systems are becoming more powerful and densely integrated, making heat management, data-processing efficiency, and packaging stability just as important as memory performance itself," Song Jai-hyuk, president and CTO of Samsung's Device Solutions division, told reporters at Computex, according to the Korea Herald 1

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Competing approaches to the same problem

While Samsung builds a route to evacuate heat away from the die-to-die hotspot, SK hynix has opted to place cooling elements directly at the problem area 1

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. SK hynix's iHBM design embeds cooling elements made of electrically non-conductive, thermally conductive silicon into the D2D PHY layer, which the company said cuts thermal resistance by more than 30% against current products 1

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. SK Hynix leverages its MR-RUF technology for iHBM DRAM production, while Samsung would likely be using proprietary in-house technologies 2

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Both methods are slated to debut with HBM5, but neither company expects mass production before 2028 1

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. First GPUs featuring HBM5 memory won't arrive until 2028-2029, giving HBM manufacturers considerable time to optimize designs while testing technologies with various partners 2

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. Song said Samsung would continue building its competitiveness in next-generation memory through cooperation with partners, including Nvidia 1

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. Samsung, SK Hynix, and Micron are currently supplying the bulk of DRAM to chipmakers powering the latest AI datacenters across the world 2

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