TSMC Eyes 20% CoWoS Price Increase as Nvidia Blackwell and Rubin Chips Strain Packaging Capacity

TSMC Considers Major CoWoS Price Hike Amid Capacity Crunch

TSMC is weighing a 10% to 20% price increase for its Chip on Wafer on Substrate (CoWoS) advanced packaging technology, according to reports from Trendforce and the Commercial Times citing supply chain sources.1

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While TSMC has not confirmed the increase, the potential hike reflects mounting supply chain pressures as surging demand for AI chips pushes packaging capacity to its limits. CoWoS packaging services combine logic dies and high-bandwidth memory (HBM) stacks within a single package, delivering the data bandwidth that AI accelerators require. This technology has become one of the tightest bottlenecks in the AI supply chain, with demand growing not just from AI GPUs but also from server CPUs and custom ASICs competing for limited capacity.1

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Nvidia Blackwell and Rubin Chips Drive Packaging Complexity

The pressure on CoWoS packaging stems largely from increasingly complex chip designs. Nvidia's Blackwell already pairs two large GPU dies with eight HBM3E stacks, while the upcoming Rubin and Rubin Ultra are expected to push integration even further.1

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Testing has emerged as another critical bottleneck. Blackwell reportedly takes three to four times longer to test than Nvidia's previous-generation Hopper, and Rubin could require as much as seven times longer.1

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Nomura Securities estimates align with these figures, noting that final testing for Blackwell takes approximately four times as long as Hopper.2

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Extended test cycles keep equipment occupied longer, making it harder to increase output as demand accelerates. Larger packages also consume more production time and resources, compounding the capacity challenge.

Equipment Lead Times Stretch to Eight Months

Equipment lead times have stretched from three to six months to as long as eight months, making timely access to fabrication tools increasingly critical.1

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TSMC has reportedly placed this year's equipment orders at existing prices without negotiating its usual discounts or extra features, signaling that securing tools on time now matters more than cost optimization.1

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This departure from TSMC's customary approach underscores the severity of the capacity crunch. Cliff Hou, deputy co-COO at TSMC, revealed in July that the company's expected equipment needs had reached 1.9 times its original estimate as AI chip demand accelerated. "Compared with the pattern 30 years ago, we have never seen the demand increase that much, that frequency of changes," Hou stated.1

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Capacity Expansion and Broader Supply Chain Moves

TSMC is working to expand its packaging capacity, though bringing new facilities to full production takes time. Industry estimates cited by Trendforce project TSMC's monthly CoWoS capacity will exceed 106,000 wafers in 2026, targeting 227,000 wafers in 2027.1

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Analysts cited by the Commercial Times expect monthly capacity to surpass 130,000 wafers in 2026 and reach 200,000 in 2027, while Goldman Sachs offers a more conservative 2026 estimate of around 106,000 wafers per month.2

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TSMC is also broadening its supply chain. Earlier this month, GlobalFoundries agreed to produce silicon interposers for TSMC's CoWoS in the U.S. under a five-year contract worth $2 billion, with production expected to ramp up in the first half of 2028.1

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However, interposers represent only one part of the packaging flow, so this agreement alone will not eliminate shortages.

Wafer Prices Also Set to Rise

The potential CoWoS price increase comes alongside broader pricing changes. TSMC is reportedly considering wafer price increases for 2027, with advanced process technologies expected to rise by 5% to 10%.1

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According to Liberty Times, TSMC has finalized plans to raise wafer prices by 3% to 6% from January 2027, with the largest increases expected for 2nm and 3nm-class nodes.2

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Customers seeking capacity beyond their original allocations may face additional premiums, potentially pushing some costs up by as much as 25%.1

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If both the packaging and wafer price increases materialize, chip designers such as Nvidia and AMD could face significantly higher production costs, and some of that will likely flow through to end customers purchasing AI hardware.