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TSMC shows smaller, faster chips without a pricey new tool from ASML
SANTA CLARA, California, April 22 (Reuters) - Taiwan Semiconductor Manufacturing Co on Wednesday showed its newest generation of chip manufacturing technology, saying it expects to be able to create smaller, faster chips without requiring expensive new machines from ASML. TSMC (2330.TW), opens new tab, the global giant that makes chips for Nvidia (NVDA.O), opens new tab, Apple (AAPL.O), opens new tab and Google (GOOGL.O), opens new tab, among many others, showed two improvements of chipmaking technology: One called A13, which will go into production in 2029 and likely be used for artificial intelligence chips, and one called N2U, a more affordable option that can be used to make chips for phones and laptops, as well as AI chips. For all of the technologies TSMC showed on Wednesday, it is planning to squeeze more gains out of its existing extreme-ultraviolet lithography (EUV) machines from Dutch supplier ASML (ASML.AS), opens new tab, rather than move to a newer generation of "high NA" EUV machines, which, at $400 million each, are roughly double the cost of the older machines. "This is where I think our R&D has done exceptionally well in terms of leveraging existing EUV technology while setting an aggressive technology scaling roadmap," Kevin Zhang, deputy co-chief operations officer and senior vice president, told Reuters. "This is definitely a strength." But the gains from smaller and faster chips are modest, and TSMC also showed plans for new technologies in stitching complex AI chips together, which is where analysts expect companies like Nvidia to get the most performance gains in coming years. Where current AI offerings like Nvidia's Vera Rubin, which will come out this year and is made by TSMC, have two large computing chips and eight stacks of high-bandwidth memory, TSMC on Wednesday said that by 2028 it will have the ability to stitch together 10 large chips and 20 memory stacks. Named after Intel CEO Gordon Moore, his eponymous law predicted that computing power would roughly double every two years while at the same time get cheaper. In recent years, some such as Nvidia's CEO Jensen Huang have said that it no longer holds true. TSMC is effectively extending Moore's law through the company's technology that stitches multiple chips together, according to Dan Hutcheson, vice chair of TechInsights. "Moore's law is morphing from a monolithic, single die in a package to multi-die in a package," he said in an interview. "And that allows the power and performance gains." But stitching together chips brings challenges of its own. The chips get hot as they operate, and the different materials used to package them together expand at different rates, creating a fresh set of challenges for chip designers. Large chip packages can bend and crack, which were issues for Nvidia's Rubin AI processor, according to Ian Cutress, chief analyst at consultancy More Than Moore. "(TSMC) aren't addressing directly how they are solving those challenges," Cutress said. Reporting by Stephen Nellis and Max Cherney in Santa Clara, California; Editing by Stephen Coates Our Standards: The Thomson Reuters Trust Principles., opens new tab * Suggested Topics: * Asia Pacific Max A. Cherney Thomson Reuters Max A. Cherney is a correspondent for Reuters based in San Francisco, where he reports on the semiconductor industry and artificial intelligence. He joined Reuters in 2023 and has previously worked for Barron's magazine and its sister publication, MarketWatch. Cherney graduated from Trent University with a degree in history.
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TSMC shows smaller, faster chips without a pricey new tool from ASML
SANTA CLARA, California, April 22 (Reuters) - Taiwan Semiconductor Manufacturing Co on Wednesday showed its newest generation of chip manufacturing technology, saying it expects to be able to create smaller, faster chips without requiring expensive new machines from ASML. TSMC, the global giant that makes chips for Nvidia, Apple and Google, among many others, showed two improvements of chipmaking technology: One called A13, which will go into production in 2029 and likely be used for artificial intelligence chips, and one called N2U, a more affordable option that can be used to make chips for phones and laptops, as well as AI chips. For all of the technologies TSMC showed on Wednesday, it is planning to squeeze more gains out of its existing extreme-ultraviolet lithography (EUV) machines from Dutch supplier ASML, rather than move to a newer generation of "high NA" EUV machines, which, at $400 million each, are roughly double the cost of the older machines. "This is where I think our R&D has done exceptionally well in terms of leveraging existing EUV technology while setting an aggressive technology scaling roadmap," Kevin Zhang, deputy co-chief operations officer and senior vice president, told Reuters. "This is definitely a strength." But the gains from smaller and faster chips are modest, and TSMC also showed plans for new technologies in stitching complex AI chips together, which is where analysts expect companies like Nvidia to get the most performance gains in coming years. Where current AI offerings like Nvidia's Vera Rubin, which will come out this year and is made by TSMC, have two large computing chips and eight stacks of high-bandwidth memory, TSMC on Wednesday said that by 2028 it will have the ability to stitch together 10 large chips and 20 memory stacks. Named after Intel CEO Gordon Moore, his eponymous law predicted that computing power would roughly double every two years while at the same time get cheaper. In recent years, some such as Nvidia's CEO Jensen Huang have said that it no longer holds true. TSMC is effectively extending Moore's law through the company's technology that stitches multiple chips together, according to Dan Hutcheson, vice chair of TechInsights. "Moore's law is morphing from a monolithic, single die in a package to multi-die in a package," he said in an interview. "And that allows the power and performance gains." But stitching together chips brings challenges of its own. The chips get hot as they operate, and the different materials used to package them together expand at different rates, creating a fresh set of challenges for chip designers. Large chip packages can bend and crack, which were issues for Nvidia's Rubin AI processor, according to Ian Cutress, chief analyst at consultancy More Than Moore. "(TSMC) aren't addressing directly how they are solving those challenges," Cutress said. (Reporting by Stephen Nellis and Max Cherney in Santa Clara, California; Editing by Stephen Coates)
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Taiwan Semiconductor Manufacturing Co revealed two new chipmaking technologies—A13 for AI chips arriving in 2029 and N2U for affordable phone and laptop processors. The company plans to leverage existing extreme-ultraviolet lithography machines rather than invest in costly upgrades, while advancing chip stitching techniques that could assemble 10 large chips and 20 memory stacks by 2028.

Taiwan Semiconductor Manufacturing Co has unveiled its latest chip manufacturing technology advancements, demonstrating a strategic approach that maximizes existing equipment rather than pursuing expensive new machinery. At a presentation in Santa Clara, California, TSMC introduced two distinct technologies: A13, slated for production in 2029 and designed primarily for AI chips, and N2U, a more affordable option targeting chips for phones, laptops, and artificial intelligence applications
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. The company, which manufactures chips for industry giants including Nvidia, Apple, and Google, is charting a path that sidesteps the need for ASML's next-generation "high NA" extreme-ultraviolet lithography (EUV) machines, which cost approximately $400 million each—roughly double the price of current models2
.TSMC's strategy centers on extracting additional performance from its current ASML EUV machines rather than investing in the newer generation of lithography equipment. Kevin Zhang, deputy co-chief operations officer and senior vice president at TSMC, emphasized the company's research and development achievements in this area. "This is where I think our R&D has done exceptionally well in terms of leveraging existing EUV technology while setting an aggressive technology scaling roadmap," Zhang told Reuters. "This is definitely a strength"
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. This approach allows TSMC to continue producing smaller, faster chips while managing capital expenditures more efficiently, a consideration that matters significantly in the semiconductor industry where equipment costs can impact pricing and competitiveness.While the gains from traditional chip miniaturization remain modest, TSMC revealed ambitious plans for advanced chip stitching technologies that industry analysts view as critical for future AI processor performance. By 2028, the company expects to possess the capability to stitch together 10 large chips and 20 memory stacks—a substantial increase from current AI offerings like Nvidia's Vera Rubin, which features two large computing chips and eight stacks of high-bandwidth memory
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. This progression in chip packages represents where companies like Nvidia are expected to achieve the most significant performance gains in coming years, as the industry shifts from relying solely on transistor density improvements to multi-chip integration strategies.Related Stories
The A13 and N2U technologies, combined with TSMC's chip stitching capabilities, effectively represent a modern interpretation of extending Moore's Law—the prediction by Intel CEO Gordon Moore that computing power would roughly double every two years while becoming more affordable. Dan Hutcheson, vice chair of TechInsights, explained that "Moore's law is morphing from a monolithic, single die in a package to multi-die in a package. And that allows the power and performance gains"
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. This shift matters because prominent figures like Nvidia CEO Jensen Huang have questioned whether Moore's Law still holds true in recent years. TSMC's approach suggests the principle continues to evolve rather than disappear, adapting to new technological realities in the semiconductor industry.Despite the promising technology scaling roadmap, the transition to more complex chip packages introduces engineering hurdles that TSMC has yet to fully address publicly. As chips operate, they generate heat, and the different materials used in packaging expand at varying rates, creating stress on the integrated components. Ian Cutress, chief analyst at consultancy More Than Moore, noted that large chip packages can bend and crack—issues that affected Nvidia's Rubin AI processor. "(TSMC) aren't addressing directly how they are solving those challenges," Cutress observed
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. These thermal and mechanical challenges will require innovative solutions as the industry pushes toward assembling increasingly complex configurations with more memory stacks and computing power concentrated in single packages. How TSMC and its clients navigate these obstacles will likely influence the pace at which advanced AI chips reach market and their reliability in demanding applications.Summarized by
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