TSMC unveils chip manufacturing technology that bypasses $400 million ASML machines

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Taiwan Semiconductor Manufacturing Co revealed two new chipmaking technologies—A13 for AI chips arriving in 2029 and N2U for affordable phone and laptop processors. The company plans to leverage existing extreme-ultraviolet lithography machines rather than invest in costly upgrades, while advancing chip stitching techniques that could assemble 10 large chips and 20 memory stacks by 2028.

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TSMC Advances Chip Manufacturing Technology Without Costly Equipment Upgrades

Taiwan Semiconductor Manufacturing Co has unveiled its latest chip manufacturing technology advancements, demonstrating a strategic approach that maximizes existing equipment rather than pursuing expensive new machinery. At a presentation in Santa Clara, California, TSMC introduced two distinct technologies: A13, slated for production in 2029 and designed primarily for AI chips, and N2U, a more affordable option targeting chips for phones, laptops, and artificial intelligence applications

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. The company, which manufactures chips for industry giants including Nvidia, Apple, and Google, is charting a path that sidesteps the need for ASML's next-generation "high NA" extreme-ultraviolet lithography (EUV) machines, which cost approximately $400 million each—roughly double the price of current models

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Leveraging Existing EUV Technology for Smaller, Faster Chips

TSMC's strategy centers on extracting additional performance from its current ASML EUV machines rather than investing in the newer generation of lithography equipment. Kevin Zhang, deputy co-chief operations officer and senior vice president at TSMC, emphasized the company's research and development achievements in this area. "This is where I think our R&D has done exceptionally well in terms of leveraging existing EUV technology while setting an aggressive technology scaling roadmap," Zhang told Reuters. "This is definitely a strength"

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. This approach allows TSMC to continue producing smaller, faster chips while managing capital expenditures more efficiently, a consideration that matters significantly in the semiconductor industry where equipment costs can impact pricing and competitiveness.

Advanced Chip Stitching Emerges as Key Performance Driver

While the gains from traditional chip miniaturization remain modest, TSMC revealed ambitious plans for advanced chip stitching technologies that industry analysts view as critical for future AI processor performance. By 2028, the company expects to possess the capability to stitch together 10 large chips and 20 memory stacks—a substantial increase from current AI offerings like Nvidia's Vera Rubin, which features two large computing chips and eight stacks of high-bandwidth memory

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. This progression in chip packages represents where companies like Nvidia are expected to achieve the most significant performance gains in coming years, as the industry shifts from relying solely on transistor density improvements to multi-chip integration strategies.

Extending Moore's Law Through Multi-Die Integration

The A13 and N2U technologies, combined with TSMC's chip stitching capabilities, effectively represent a modern interpretation of extending Moore's Law—the prediction by Intel CEO Gordon Moore that computing power would roughly double every two years while becoming more affordable. Dan Hutcheson, vice chair of TechInsights, explained that "Moore's law is morphing from a monolithic, single die in a package to multi-die in a package. And that allows the power and performance gains"

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. This shift matters because prominent figures like Nvidia CEO Jensen Huang have questioned whether Moore's Law still holds true in recent years. TSMC's approach suggests the principle continues to evolve rather than disappear, adapting to new technological realities in the semiconductor industry.

Technical Challenges Remain for Complex Chip Packages

Despite the promising technology scaling roadmap, the transition to more complex chip packages introduces engineering hurdles that TSMC has yet to fully address publicly. As chips operate, they generate heat, and the different materials used in packaging expand at varying rates, creating stress on the integrated components. Ian Cutress, chief analyst at consultancy More Than Moore, noted that large chip packages can bend and crack—issues that affected Nvidia's Rubin AI processor. "(TSMC) aren't addressing directly how they are solving those challenges," Cutress observed

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. These thermal and mechanical challenges will require innovative solutions as the industry pushes toward assembling increasingly complex configurations with more memory stacks and computing power concentrated in single packages. How TSMC and its clients navigate these obstacles will likely influence the pace at which advanced AI chips reach market and their reliability in demanding applications.

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