XCENA raises $135M on a bet that AI's real bottleneck is memory, not compute

This chip startup just raised $135M on a bet that AI's biggest bottleneck isn't compute -- it's memory

Every time you ask ChatGPT a question, your request triggers a data relay race. Information leaves memory, passes through a CPU for preprocessing, travels to a GPU for heavy computation, and then makes its way back -- and that entire journey repeats for every single word the AI generates. The bottleneck is structural -- it means routing through some of the most expensive and power-intensive chips in the industry on every single request. That inefficiency is exactly what XCENA, a startup with offices in South Korea and the U.S., is trying to solve. The four-year-old startup has designed a chip that places compute capabilities much closer to DRAM -- the fast, short-term memory chips that store data a processor is actively using -- allowing routine data operations to be handled near memory, without the costly round trips between CPUs, GPUs, and memory. If it works at scale, the implications for AI infrastructure costs could be significant, which largely explains investor enthusiasm around the country. Indeed, XCENA just raised $135 million in a Series B at a valuation of $570 million, bringing its total raised to $185 million. XCENA CEO Jin Kim co-founded the startup in 2022 alongside CTO Dohun Kim and CPO Harry Juhyun Kim, all veterans of Samsung and SK Hynix, the memory giants that supply chips powering Nvidia's GPUs. "CPUs and GPUs have both gotten smarter over the decades. Memory never did. XCENA wants to change that," Kim said in an interview with TechCrunch. "The recent rise in memory prices and related stocks points to a broader shift in AI infrastructure toward memory-centric architectures," he added. (This month, the three companies that dominate the global memory chip market -- Samsung, SK Hynix, and Micron -- each crossed a trillion-dollar valuation for the first time.) XCENA is betting its business on the thesis that "inference isn't just a compute problem; it's increasingly a memory scaling problem," said Kim. XCENA's chip, the MX1, connects to the CPU through CXL (Compute Express Link) -- essentially a dedicated express lane between the processor and memory -- processing data before it ever needs to leave the memory module. It brings compute to the data, not the other way around. The company claims that what used to require 10 servers could potentially run on just one. "While GPUs excel at matrix multiplication -- the heavy math behind AI model training -- much of the surrounding data orchestration, including preprocessing, KV cache management [the system that stores prior conversation context so a model doesn't have to reprocess it], and data caching, still runs on CPUs. Our chip handles those tasks directly within the memory module itself," Kim said. Demand for memory solutions has surged since the second half of last year, and the company believes the timing is working in its favor. Conversations with several global memory vendors are in early stages, though Kim declined to name them. The company's ideal customers are hyperscalers spending tens of billions a year on AI infrastructure, where even a small gain in memory efficiency can mean hundreds of millions in savings. The MX1 is still a prototype. Mass production chips are scheduled to roll off Samsung's foundry lines by the end of 2026, with the company expecting to generate revenue starting in 2027. While neural processing unit (NPU) makers are competing to challenge Nvidia for training workloads, XCENA is targeting the memory-intensive layer that sits underneath all of it. XCENA's closest rivals include Astera Labs and Marvell, both Nasdaq-listed companies working on next-generation memory connectivity. Marvell is a large, established player already working in the same space, Kim said, adding that the differentiator comes down to intellectual property. "We have thousands of cores," Kim said. Based on public specs, Marvell's approach relies on a handful of general-purpose cores by comparison. Those cores are built on RISC-V -- an open-source chip design blueprint -- and optimized specifically for data processing, with each core deliberately kept small and efficient. Beyond the cores themselves, XCENA designs its own internal memory hierarchy, interconnect bus, and DRAM controller -- a level of vertical integration that most chip companies, including larger rivals, typically outsource. Seoul-based VC firms Altinum and IMM Investment co-led the Series B round, along with Corstone Asia and existing investors SBI Investment and Mirae Asset Capital. The company, which has more than 90 staff across offices in Pangyo, a tech hub outside Seoul, and in Sunnyvale, is also in conversations with international investors about additional funding.

XCENA raises $135M for its computational memory controller

XCENA Inc., a startup with a memory device designed to speed up artificial intelligence clusters, today announced that it has raised $135 million in funding. The Series B round was led by Korean funds Atinum Investment and IMM Investment. XCENA says that the raise also included contributions from more than a half dozen other institutional backers. The company is now valued at $570 million. XCENA was founded in 2022 by former employees of Samsung Electronics Co. and SK hynix Inc., the world's top suppliers of memory for graphics cards. XCENA's flagship product is a device called the MX1 that it describes as a computational memory controller. It's designed to speed up the data management tasks involved in running AI inference workloads. Large language models use a data structure called a KV cache to interpret user prompts. When the KV cache can't fit in a graphics card's built-in memory, it has to be offloaded to slower external DRAM, which creates processing delays. A similar issue affects the vector databases that many LLMs use to store information. XCENA says that the MX1 addresses the challenge. The device combine up to two terabytes of DRAM with several thousand central processing unit cores. According to XCENA, it can hold an LLM's KV cache and vector databases without the performance issues that affect traditional memory devices. The result is an increase in inference performance. Another way the device accelerates AI workloads is by reducing the need for duplicate calculations. Many LLMs refresh their KV cache, the data structure they use to interpret prompts, after every user request. MX1 makes it possible to reuse the same KV cache across requests and thereby reduce processing overhead. The company says the chip can also accelerate analytics applications such as Apache Spark. Such workloads regularly move data between the CPUs on which they run and the memory they use to hold data. The MX1's memory pool and CPU cores are closer to each other than the components of a standard server, which reduces data travel times. The device's CPU cores are based on the open-source RISC-V architecture. They're organized into four-core clusters that each have a dedicated L1 cache, a type of high-speed memory. The four-core clusters are organized into larger clusters that likewise have an integrated memory pool. XCENA provides application programming interfaces that enable developers to port their AI workloads to the MX1 without major code changes. According to the company, customers with more advanced requirements have access to a second set of APIs that can be used to make low-level performance optimizations. XCENA also provides a simulation tool that eases software reliability testing. The company plans to make the MX1 using Samsung's four-nanometer chip manufacturing process. According to TechCrunch, XCENA will begin mass production by the end of the year and expects to start generating revenue in 2027. The company will use the proceeds from its funding round to develop new computational memory products. In addition, XCENA plans to accelerate its go-to-market efforts and establish partnerships with key industry players such as hyperscalers.