AMD Unveils EPYC Verano: Zen 6 Processor With Up to 192 Cores and LPDDR5X Memory for AI Infrastructure

AMD EPYC Verano Targets AI Infrastructure With Zen 6 Architecture

AMD provided the first look at its AMD EPYC Verano processor during the OCP Global Summit 2026, marking a strategic shift in server CPU design specifically engineered for AI infrastructure1

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. The next-generation EPYC CPU belongs to AMD's sixth-generation EPYC family and utilizes Zen 6 technology, but diverges from conventional server processors by prioritizing power-efficient memory and communication with GPU accelerators. Lisa Su, AMD CEO, displayed Verano silicon during her keynote and explained how the processor fits into the company's upcoming AI infrastructure platforms, describing it as "the next step in AMD's CPU roadmap for the AI era"2

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. The chip is designed to serve as a host CPU for future AMD Instinct accelerators, including the MI500 series, handling general-purpose processing tasks necessary to keep large GPU installations operating efficiently1

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LPDDR5X Memory Through SOCAMM2 Modules Debuts on EPYC Platform

One of Verano's defining features is its support for LPDDR5X memory using SOCAMM2 modules, marking AMD's first announced EPYC implementation of this memory standard1

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. While traditional EPYC platforms use DDR5 RDIMMs or MRDIMMs, Verano introduces a memory configuration aimed at reducing power consumption while maintaining the bandwidth required by accelerator-based computing platforms. SOCAMM2 combines LPDDR technology with a removable module design, addressing a longstanding limitation where LPDDR memory is often soldered directly to motherboards, complicating servicing and repairs1

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. The compact connection makes modules replaceable without permanently attaching memory devices to the system board. This approach could prove valuable in densely configured AI servers, where memory power consumption contributes significantly to overall rack-level energy requirements. AMD is positioning Verano around performance per system watt rather than simply increasing traditional CPU benchmark performance1

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Core Count Specifications Show Up to 192 Cores Configuration

The processor's core configuration has attracted considerable attention, with conflicting reports emerging about its capabilities. Earlier reporting indicated that Verano would feature up to 72 cores Zen 6 cores alongside a 24-channel LPDDR5X memory configuration1

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. However, more recent information from the OCP Global Summit 2026 suggests AMD demonstrated a processor featuring as many as up to 192 cores1

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. The discrepancy could reflect separate configurations, with the larger count potentially representing a dual 96-core setup rather than a single chip2

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. AMD has not yet released comprehensive product specifications covering the entire Verano lineup, leaving questions about individual core counts, clock frequencies, cache capacities, and power requirements unanswered. The chip shown during the event featured eight Zen 6 CCDs with two large IO dies and four LP5X memory controllers on the outskirts2

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Verano Designed to Accelerate Agentic AI Workloads

AMD EPYC Verano CPUs are part of the EPYC 9006 LP family and will be configured on the SP8 platform, specifically tailored to accelerate agentic AI workloads2

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. The processor is reportedly designed to support xGMI communication speeds reaching up to 112 Gbps, with the technology intended for future Instinct GPU installations to feed Instinct MI500 GPUs in next-generation AI racks1

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. This high-speed interconnect capability positions Verano as a critical component in AMD's broader AI infrastructure strategy. The processor is expected to become available during the first half of 20271

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. Compared to the EPYC Venice "Zen 6C" chip, the CCDs appear smaller, suggesting these could be the standard 12-core "Zen 6" dies instead of the denser 32-core "Zen 6C" variants2

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Competitive Landscape Intensifies in AI-Optimized Server Market

The introduction of Verano comes as competition intensifies in the AI-optimized server processor space. Like AMD, NVIDIA Vera Rubin and Vera CPX platforms also feature SOCAMM2 LPDDR5X memory, while LPDDR has become the prime choice for several upcoming AI accelerators, including Tesla's A15 and several Intel AI accelerators focused on inference-optimized GPU solutions2

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. AMD faces mounting competition from NVIDIA, Intel, Qualcomm, Arm, and multiple others rolling out their own agentic AI-optimized chips2

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. During her keynote, Lisa Su pointed out that the server CPU market demand is expected to grow by 50% by 2030, hitting $200 billion2

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. Given AMD's success with EPYC and its solidifying CPU position over recent years, these next-generation Zen 6 and upcoming Zen 7/Zen 8 lineups could capture significant market share. Watch for detailed bandwidth specifications, platform topology disclosures, and competitive responses from Intel and NVIDIA as the 2027 launch approaches. The adoption rate of SOCAMM2 modules across the industry will signal whether AMD's bet on removable LPDDR5X memory becomes a new standard for AI infrastructure.