AMD unveils EPYC Venice with 256 Zen 6 cores, first 2nm chip built for agentic AI era

AMD EPYC 9006 Venice Announced & Looks Poised To Be A Grand Slam

While AMD EPYC 9005 "Turin" launched just under two years ago, it has aged remarkably well. It is one of the few CPU generations in my past 22 years of Linux hardware reviews/benchmarking that has still captivated me two years on in finding still typically industry-leading performance across varying workloads, exceptional reliability, and all around a very robust platform. Today though at AMD Advancing AI 2026, Lisa Su formally announced EPYC 9006 "Venice" for taking their server offerings to the next level in the agentic AI era. Part of what made AMD EPYC 9005 rather timeless is that it has performed incredibly well against the competition. Even for more recent CPUs like NVIDIA Vera or EPYC Turin outperforming Amazon's new Graviton5, Turin has aged superb. Yet here we are with EPYC Venice in production. Against Intel Xeon 6 Granite Rapids, the advantage with Intel has been MRDIMMs for greater memory bandwidth in memory intensive workloads over DDR5-6400 (albeit with greater power and cost) or workloads prepared to make use of Advanced Matrix Extensions (AMX). With EPYC Venice, AMD is now supporting Gen2 MRDIMM-12800 memory as well as DDR5-8000 memory. That right there eliminates Granite Rapid's advantage with just leaving AMX for select AI workloads as a unique trait. While AMD EPYC 9006 series does not support AMX, Venice does improve AMD's AVX-512 support with AVX-512 BMM. That will be interesting to benchmark the AVX-512 BMM impact in future articles on Phoronix with up-to-date compilers. Beyond DDR5-8000 and MRDIMM-12800 MT/s speeds, EPYC Venice supports up to 16 channel memory per socket. Given EPYC 9005 Turin's performance advantage overall, pair that with around 20% more performance per core for a total knockout. Even for workloads like Nginx HTTPS web serving, AMD demonstrated 1.2x gen-on-gen performance. And with Zen 6C up to 256 cores / 512 threads per socket. AMD EPYC 9006 Venice also supports PCIe Gen 6 with up to 160 lanes in a dual socket configuration. There are also new power management features with Venice like FAST, UBPS, and UPP that will be fun to test and evaluate. EPYC Venice clock frequencies will top out at 5.0GHz for the 96 core processor. Venice is made up of EPYC 9006 SP7 processors, EPYC 9006 SP8 for more optimized server value, and EPYC 9006X SP7 for the Venice-X 3D V-Cache processors that will debut in 2027. AMD EPYC 9006 LP "Verano" is also on the way for EPYC Zen 6 with LPDDR memory in the second half of 2027. While "announced" today, during the embargoed briefings in San Francisco, no EPYC 9006 SKU tables or the like were shared and EPYC 9006 SP7 won't be available until Q4. So for some it will be viewed as more of a soft launch. But considering how strong EPYC 9005 series is performing, even if AMD's claims are only half-way met, which would be unusual, it would still come out as industry leading given the current strong performance out of EPYC 9005. Benchmarks of AMD EPYC 9006 Venice will be happening on Phoronix soon. And unlike all of the hand-holding, selected benchmark restrictions, and preventing of power/frequency reporting as recently noted with NVIDIA Vera, there will not be any such restrictions with EPYC Venice. AMD is committed to fairly show they can deliver in today's diverse agentic AI era and even with more traditional Linux server workloads, HPC, etc. From the numbers presented by AMD of EPYC Venice, the processor is delivering decisive wins over the Intel Xeon and ARM server CPU competition, which even if interpreted rather conservatively on the side of caution should still be very strong and excellent shape considering the current dominating position with EPYC 9005 Turin. Furthermore, Intel's competition with Xeon Diamond Rapids isn't coming out until at least 2027. Very interesting times ahead in the Linux server space.

AMD's 256-core EPYC Venice die shot has been spotted on Moscone Center banners ahead of Lisa Su's keynote

Ahead of CEO Lisa Su's Advancing AI 2026 keynote in San Francisco, AMD has begun showcasing its upcoming EPYC Venice processor. Banners installed around the Moscone Center West, photographed by ComputerBase, include a detailed rendering of the flagship 256-core Venice chip's internal layout, and it is a genuinely impressive piece of silicon. The die shot confirms the structure AMD teased at CES earlier this year. Eight compute dies surround two large I/O dies at the center. Each compute die is a CCD containing two 16-core Core Complexes, giving each CCD 32 cores. Eight CCDs across 16 CCXs add up to 256 cores and 512 threads in the flagship configuration. The rendering shows cores arranged in a 2x4x4 layout within each CCD, consistent with the dense Zen 6c configuration used in the highest core count Venice processors rather than the larger standard Zen 6 cores. Venice is the first high-performance computing product to enter volume production on TSMC's 2nm process, which transitions from FinFET to Nanosheet transistors and delivers 10 to 15% higher performance at the same power, 25 to 30% lower power consumption at the same performance, and up to 15% higher transistor density. AMD has promised more than 70% performance and efficiency improvement over its current generation EPYC Turin chips, alongside a more than 30% increase in thread density. Agentic AI and reinforcement learning workloads are driving demand for high core count, high throughput server CPUs in a way that is pulling investment toward that space alongside GPUs. NVIDIA's Vera CPU is AMD's primary competitor here, and AMD has shown early benchmarks placing Venice well ahead. More details are expected during Lisa Su's keynote, where AMD is also expected to address its Helios rack-scale AI platform.

AMD's Zen 6 EPYC Venice Pictured as a 256-Core Monster, Massive Twin I/O Dies & First 2nm HPC Chip To Enter Volume Ramp

AMD has showcased its next-generation EPYC Venice CPU at the Advancing AI event, featuring a phenomenal core count of 256 based on Zen 6. AMD Is Firing Across All Cylinders With Its Next-Gen EPYC Venice CPU Lineup: Flagship With 256 "Zen 6" Cores Pictured & It's A Monster Chip For the next stream of data centers, CPUs are going to play a much more important role than GPUs due to the rise in Agentic AI & RL workflows. As such, all CPU vendors are releasing brand new chips that unleash the best capabilities for these workloads while leading the charts against the competition. At Advancing AI 2026, AMD has confirmed to launch its EPYC Venice CPUs based on the Zen 6 core architecture. But while there are still a few hours left in the official presentation, the company has set banners across the Moscone Center West in San Francisco, US. One of these banners featured a very peculiar-looking chip as spotted by Computerbase, and it turns out to be none other than the flagship 256-core EPYC champion. AMD is leveraging its brand new Zen 6 core architecture that will be used on its 6th Gen EPYC CPUs, codenamed Venice. AMD's EPYC Venice chips are the first HPC product to enter volume production on TSMC's 2nm process technology, and their readiness for Helios AI racks proves that AMD will always deliver the best of the best for its high-performance customers. The TSMC 2nm process technology transitions from FinFET to Nanosheet transistors (GAA), and offers 10-15% higher performance at the same power, 25-30% lower power consumption at the same performance, and up to 15% higher transistor density. AMD's 6th Gen EPYC Venice CPUs were teased earlier this year at CES, offering up to 256 cores and 512 threads with eight massive compute dies and two even larger I/O dies. You can also see that each of the eight massive CCDs features a total of 32 cores, sliced into two 16-core complexes. The IO chips in the middle look massive in size, with lots of controllers such as PCIe 6.0, UCIe, DDR5, and more. For this chip, AMD has promised over 70% performance & efficiency improvement with its EPYC Venice CPUs, with a >30% increase in thread density. Once again, the requirement for high-performance CPUs has risen tenfold with Agentic AI workloads. And competitors are firing across all cylinders with CPUs that are optimized around agents. Just like GPUs, NVIDIA is AMD's primary competitor in this space, which is leveraging Vera CPUs based on its custom Arm IP to power the Vera Rubin NVL72 racks. AMD's Helios AI racks powered by Zen 6 EPYC chips not only offer more cores, but faster performance and improved single-core capabilities, which is important for sustained throughput. In early benchmarks, AMD has shown that not only do its 5th Gen Turin "Zen 5" CPUs lead against Vera, but the 6th Gen Venice "Zen 6" chips lead massively, driving more performance & offering better TCOs at a similar power scale. AMD EPYC CPU Families: Follow Wccftech on Google to get more of our news coverage in your feeds.