AMD splits Zen 7 into three EPYC families for 2028 as it pushes deeper into AI server market

AMD splits Zen 7 into three EPYC families for 2028 and starts selling server CPUs by the agent -- Florence, Ferrara, and Fidenza to be applied across AI-focused product stack

AMD used its recent Advancing AI 2026 event in San Francisco to launch sixth-gen EPYC "Venice" processors, Instinct MI400 Series GPUs, and Helios rack-scale systems, and to confirm that the Zen 7 generation arriving in 2028 will launch as three separate EPYC families rather than one. The company named Florence, Ferrara, and Fidenza in its launch release, extended its annual CPU, GPU, networking, and rack cadence out to 2030, and put its total addressable market at roughly $2 trillion in 2030. It also introduced a competitive yardstick it hasn't used before, claiming the most AI agents per watt, per dollar, and per rack, though its own endnotes state those agent counts are estimated from CPU thread resources used as a proxy. Three Zen 7 CPUs Florence carries fresh Zen 7 cores, a new set of AI compute extensions, and support for newer memory technologies, AMD chair and CEO Lisa Su said during the keynote. Ferrara is the AI host node portion, and it appears a second time further along the roadmap as the CPU inside the Helios 600 rack alongside MI600 Series GPUs and Pensando "Palma" and "Levanzo" networking. Fidenza, meanwhile, is the agentic sandbox product. AMD disclosed no core counts, no process node, and no socket for any of the three, and said only that Zen 7 uses leading-edge process technology. The fourth-gen EPYC generation, built on Zen 4, spanned Genoa, Bergamo, Genoa-X, and Siena across two sockets. The fifth-gen "Turin" generation then went the other way, folding Zen 5 and Zen 5c parts into a single 27-SKU stack on one socket with no separate cache-stacked or edge line at launch. Venice restarts the fan-out, with the 9006 series on the new SP7 socket now, and Venice-X arriving in 2027 with 1,152MB of 3D V-Cache, 96 cores, and a 5.15 GHz boost clock. Three named Zen 7 families at announcement, two years out, is a wider spread than AMD has ever opened a generation with. AMD's own portfolio endnote describes the EPYC range as covering general-purpose enterprise, cloud, telecom, SMB, and HPC systems, plus, as a distinct category, sandboxed agentic AI deployments and GPU head node servers. Su told analysts in May that AMD was already working with customers on architectures beyond Venice, without naming categories at the time. The Zen 7 lineup puts a name to those two AI-specific segments for the first time. Agents per rack AMD's main server CPU claim at the event is that sixth-gen EPYC enables the most agents per watt, per dollar, and per rack. Endnote 9xx6-012 in the launch release states that agent counts are estimates derived from available CPU thread resources used as a proxy under a consistent theoretical workload, and that real capacity varies with workload, model, memory, software, orchestration, and system configuration. The per-rack comparison behind it is core count at a 100 kW rack power envelope, pitting the 256-core EPYC 9996 against an 88-core Nvidia Vera, AMD's own 192-core EPYC 9965, and Intel's 128-core Xeon 6980P. The per-dollar metric is based on top-of-stack thread count divided by the 1,000-unit list pricing. The per-watt comparison in that endnote lists Nvidia Vera at 450W and Arm's AGI CPU at 300W with one thread per core, alongside Intel's Xeon 6980P at 500W and AMD's EPYC 9965 at 500W. AMD had already claimed a 3.3 times rack-level advantage over Vera in June. Mercury Research put AMD at a record 46.2% of x86 server CPU revenue in Q1 2026, against 33.2% of units, and Arm-based designs took roughly 17.7% of server shipments in the same quarter, so the widening comparison shows where these units are going. Starting with sixth-gen EPYC, AMD has replaced TDP with a figure it calls Default CPU Power, defined as total power consumed across the processor's compute and I/O dies at a stated performance target. AMD says both references can serve for product comparison and performance-per-watt analysis, and the endnote itself mixes the two conventions, quoting the EPYC 9956 at 400W Default CPU Power against TDP figures for the Nvidia, Intel, and Arm parts. 2030 cadence Helios racks pair 72 Instinct MI455X GPUs with 18 Venice CPUs, 31TB of HBM4, and 1.4 PB/s of aggregate memory bandwidth, and are in production now. AMD claims up to 30% more inference tokens per dollar than Nvidia's Vera Rubin NVL72, based on AMD Performance Labs estimates from July 2026 using a Kimi K2 Thinking workload at 32K input and 8K output, with hourly GPU pricing projections. The 34-times token throughput gain AMD quotes for MI455X over MI355X comes from AMD's own measurements on DeepSeek V4 Flash at FP4. Both, however, are vendor-provided benchmarks with no independent verification yet. The forward roadmap runs MI500 Series GPUs in 2027 inside a Helios 500 rack built on EPYC "Verano" and Pensando "Como" and "Monza" networking, MI600 Series in 2028 inside Helios 600 on Ferrara, and Ravenna on Zen 8 in 2030. OpenAI expects to bring Helios online from the fourth quarter of 2026, with deployments accelerating through 2027, while Meta is validating sixth-gen EPYC platforms in its labs and has begun testing Helios racks. Anthropic committed the day before the keynote to up to 2GW of MI455X GPUs in Helios systems, with the first gigawatt due in the first half of 2027. SemiAnalysis reported in February that manufacturing delays would push mass production and first production tokens on an MI455X UALoE72 system to Q2 2027; AMD software chief Anush Elangovan publicly rejected that assessment and said Helios remained on target for 2H 2026. AMD's cautionary statement in the launch release lists the availability of essential components, naming memory supply specifically, among the risk factors that could cause results to differ from its projections. A Helios rack carries 31 TB of HBM4, and DRAM contract prices roughly doubled quarter-on-quarter in Q1 2026 before rising again in Q2.

AMD EPYC 9006 Venice Announced & Looks Poised To Be A Grand Slam

While AMD EPYC 9005 "Turin" launched just under two years ago, it has aged remarkably well. It is one of the few CPU generations in my past 22 years of Linux hardware reviews/benchmarking that has still captivated me two years on in finding still typically industry-leading performance across varying workloads, exceptional reliability, and all around a very robust platform. Today though at AMD Advancing AI 2026, Lisa Su formally announced EPYC 9006 "Venice" for taking their server offerings to the next level in the agentic AI era. Part of what made AMD EPYC 9005 rather timeless is that it has performed incredibly well against the competition. Even for more recent CPUs like NVIDIA Vera or EPYC Turin outperforming Amazon's new Graviton5, Turin has aged superb. Yet here we are with EPYC Venice in production. Against Intel Xeon 6 Granite Rapids, the advantage with Intel has been MRDIMMs for greater memory bandwidth in memory intensive workloads over DDR5-6400 (albeit with greater power and cost) or workloads prepared to make use of Advanced Matrix Extensions (AMX). With EPYC Venice, AMD is now supporting Gen2 MRDIMM-12800 memory as well as DDR5-8000 memory. That right there eliminates Granite Rapid's advantage with just leaving AMX for select AI workloads as a unique trait. While AMD EPYC 9006 series does not support AMX, Venice does improve AMD's AVX-512 support with AVX-512 BMM. That will be interesting to benchmark the AVX-512 BMM impact in future articles on Phoronix with up-to-date compilers. Beyond DDR5-8000 and MRDIMM-12800 MT/s speeds, EPYC Venice supports up to 16 channel memory per socket. Given EPYC 9005 Turin's performance advantage overall, pair that with around 20% more performance per core for a total knockout. Even for workloads like Nginx HTTPS web serving, AMD demonstrated 1.2x gen-on-gen performance. And with Zen 6C up to 256 cores / 512 threads per socket. AMD EPYC 9006 Venice also supports PCIe Gen 6 with up to 160 lanes in a dual socket configuration. There are also new power management features with Venice like FAST, UBPS, and UPP that will be fun to test and evaluate. EPYC Venice clock frequencies will top out at 5.0GHz for the 96 core processor. Venice is made up of EPYC 9006 SP7 processors, EPYC 9006 SP8 for more optimized server value, and EPYC 9006X SP7 for the Venice-X 3D V-Cache processors that will debut in 2027. AMD EPYC 9006 LP "Verano" is also on the way for EPYC Zen 6 with LPDDR memory in the second half of 2027. While "announced" today, during the embargoed briefings in San Francisco, no EPYC 9006 SKU tables or the like were shared and EPYC 9006 SP7 won't be available until Q4. So for some it will be viewed as more of a soft launch. But considering how strong EPYC 9005 series is performing, even if AMD's claims are only half-way met, which would be unusual, it would still come out as industry leading given the current strong performance out of EPYC 9005. Benchmarks of AMD EPYC 9006 Venice will be happening on Phoronix soon. And unlike all of the hand-holding, selected benchmark restrictions, and preventing of power/frequency reporting as recently noted with NVIDIA Vera, there will not be any such restrictions with EPYC Venice. AMD is committed to fairly show they can deliver in today's diverse agentic AI era and even with more traditional Linux server workloads, HPC, etc. From the numbers presented by AMD of EPYC Venice, the processor is delivering decisive wins over the Intel Xeon and ARM server CPU competition, which even if interpreted rather conservatively on the side of caution should still be very strong and excellent shape considering the current dominating position with EPYC 9005 Turin. Furthermore, Intel's competition with Xeon Diamond Rapids isn't coming out until at least 2027. Very interesting times ahead in the Linux server space.

AMD's 6th Gen EPYC lineup splits four ways -- and the power spec changed, too

His love of PCs and their components was born out of trying to squeeze every ounce of performance out of the family computer. Tinkering with his own build at age 10 turned into building PCs for friends and family, fostering a passion that would ultimately take shape as a career path. Besides being the first call for tech support for those close to him, Ty is a computer science student, with his focus being cloud computing and networking. He also competed in semi-pro Counter-Strike for 8 years, making him intimately familiar with everything to do with peripherals. At its Advancing AI 2026 event in San Francisco, AMD has officially unveiled their 6th Gen EPYC server processors, positioning them as four distinct families rather than the single 256-core flagship that has dominated pre-launch coverage. The EPYC 9006 Series spans the 9006 SP7, 9006 SP8, 9006X SP7 and 9006 LP, each matched to a different job in the data center. The EPYC family grows Four different jobs for four different processors The flagship 6th Gen EPYC 9006 SP7 anchors the top of the stack with up to 256 cores and 512 threads, built for high-density agent sandbox execution. In high-frequency configurations, it doubles as an AI host node, reaching up to 5GHz with best-in-class PCIe Gen 6 connectivity. The 9006X SP7 targets HPC, technical computing and data-intensive workloads, carrying three times the L3 cache per core of the base 9006 SP7, with some variants reaching 5.15GHz. AMD points it at simulation, modeling, in-memory analytics and other memory-sensitive work. The 9006 SP8 covers right-sized deployments with 8- to 128-core options and low-power designs, aimed at edge sites, power-constrained racks, smaller clusters and general-purpose servers. Finally, the fourth processor, the 9006 LP, was previously codenamed Verano. AMD describes it as a purpose-built AI host node CPU using LPDDR memory and enhanced XGMI to keep accelerators fed across dense, accelerator-rich racks. The flagship 9006 SP7 is in production and is expected to begin shipping in Q4 of 2026, while the other three processors are shipping in 2027. Also starting with this generation is a new power metric. AMD has begun to use Default CPU Power rather than its historical TDP reference. The figure reflects total power consumed across the processor's compute and I/O dies at a stated performance target. AMD says both measures can still serve for product comparison and platform planning, but they are not defined identically. In fact, the company's own footnotes list the 6th Gen EPYC 9956 at 400W Default CPU Power against the 5th Gen 9965 at 500W TDP.

AMD confirms Zen 7 Epyc "Florence" for 2028 and previews Zen 8 Epyc "Ravenna" for 2030

Serving tech enthusiasts for over 25 years. TechSpot means tech analysis and advice you can trust. The big picture: AMD had a busy week, announcing the Ryzen 7 7700X3D CPU for gaming PCs and the Epyc Venice lineup for agentic AI workloads in data centers and high-end workstations. The company also launched the Helios rack-scale AI system at its Advancing AI 2026 event in San Francisco and previewed its next-generation Zen 7 and Zen 8 CPU architectures. In her keynote speech, AMD CEO Lisa Su revealed that Zen 7 will debut in 2028 with the 7th-generation Epyc "Florence" processors for enterprise and AI data centers. The new core architecture will be divided into classic (Zen 7) and compute-optimized (Zen 7c) versions, with both expected to be manufactured on TSMC's cutting-edge A16 or A14 process node. AMD did not reveal any architectural details about Zen 7, but confirmed that Epyc Florence will include both Zen 7 and Zen 7c cores. The Florence processors will also be the first processors in AMD's portfolio to support the next iterations of MRDIMM and LPDDR memory standards, as well as ACE AI Compute Extensions to accelerate matrix multiplication and AI workloads across the x86 ecosystem. Epyc Florence will cover the existing SP7 and SP8 platforms, with the SP7 chips delivering high-core-count and flagship performance, while the SP8 versions will offer optimized performance with a focus on value. Both versions will power AMD's next-gen AI rack solution, "Ferrara," which will be optimized for high-performance AI host nodes. Moving beyond Zen 7, AMD added that it has started work on its Zen 8 core architecture, which will debut in 2030 with the company's 8th-generation Epyc chips, codenamed "Ravenna." The company did not reveal anything else about either Zen 8 or Epyc Ravenna, including architectural details, process node, core count, or memory support. Team Red also unveiled the Instinct MI455X AI accelerator with CDNA 5 compute architecture and confirmed that the CDNA 6-based MI500 will debut in 2027, followed by the MI600 in 2028. The company has yet to confirm the CDNA generation, memory configurations, and compute specifications for the MI600. Moving to the Helios AI rack roadmap, the first-generation models are set to launch this year, powered by Epyc Venice CPUs and the new MI455X accelerator. Helios 500 is slated to arrive in 2027 with Epyc Verano CPUs and Instinct MI500 GPUs, followed by Helios 600 in 2028, powered by Epyc Ferrara and Instinct MI600. Earlier this week, AMD launched its latest 3D V-Cache CPU, the Ryzen 7 7700X3D. Aimed at gamers on a budget, the new processor comes with 8 Zen 4 cores, 16 threads, and 96MB of L3 cache. The company also unveiled the Zen 6-based Epyc Venice CPUs and revealed key details about its Arm-based Vera CPU, designed specifically for agentic AI workloads in data centers.

AMD's Venice is the first 2nm x86 server chip, but the stack doesn't fully ship until 2027

* AMD EPYC 9006 "Venice" offers mammoth 256-core, 512-thread configuration that incorporates up to 1GB of L3 cache and PCI-E 6.0 and 16 DDR5 memory channels under the hood * It's the first time AMD's EPYC lineup sees high core count CPUs push past the 5GHz barrier * AMD is claiming a win by stating that its newest EPYC CPU offers the "most agents per watt, per dollar, per rack" AMD's newly-announced 6th Gen EPYC 9006 "Venice" seems to be a genuine silicon milestone (the first x86 server CPU on a 2nm-class node, up to 256 cores and 512 threads) which sees the company aim to secure its position in the AI data center CPU market. The launch comes at a time when AMD has caught Intel on the back foot but finds its position threatened in turn by Nvidia's Vera CPU, which it touts as a faster, more efficient alternative to traditional x86 offerings, including AMD's own EPYC lineup. With a staggered launch in place for the four CPUs AMD showcased at the AAI event, the stack is expected to be fully available to consumers sometime in 2027, even as its beefy 256-core CPU targets a Q4 2026 launch. A massive upgrade on multiple fronts AMD's Venice is a serious generational step. It is built on TSMC's N2 process, the foundry's first move from FinFET to gate-all-around nanosheet transistors, and Team Red says the family is the first high-performance computing product in the industry to reach volume production on the node. AMD's recently announced flagship model, the 256-core, 512-thread EPYC 9996, features its new SP7 socket, offering 16-channel DDR5 memory, PCIe 6.0 support, and boost clocks that push past 5GHz. This effectively doubles what is currently on offer for AMD's current-gen EPYC CPUs: memory moves to 16 channels of DDR5-8000, or MRDIMM at 12,800 MT/s, for roughly 1.6 TB/s per socket. AMD goes one step further with the 9006X lineup (expected 2H 2027), which replaces the cores it cuts down on with a much larger L3 cache per core, a design that it touts makes it much better than rivals at workflows including HPC, technical computing, and data-intensive workloads, which benefit from the larger cache (and memory bandwidth) on offer. "6th Gen AMD EPYC delivers workload-optimized compute for the full spectrum of modern data center needs; from running more agents and feeding GPUs across rack-scale AI infrastructure to powering the business-critical applications and services organizations rely on every day," noted SVP & GM of Compute and Enterprise AI at AMD, Dan McNamara. AMD argues that the shape of the data center is changing into a three-tier agentic architecture, with each tier creating distinct CPU demand, which results in workflows centering around agent sandbox execution, AI host nodes, and general-purpose servers, all of which its EPYC CPUs are designed to handle. The EPYC 9006 series also powers AMD's rack-scale Helios, as it aims to take on Nvidia's Vera Rubin NVL72 rack-scale offering with its own solution. With AMD also offering a more mainstream 9006 SP8 and the EYPC 9006 LP as an AI host node CPU that uses LPDDR memory, it is aiming to capture all ends of the AI data center CPU market and cement its current lead in a segment that is sure to be increasingly competitive in the days to come. Follow TechRadar on Google News and add us as a preferred source to get our expert news, reviews, and opinion in your feeds.

AMD Maps EPYC and Instinct Generations Through 2030 With Zen 8

AMD has extended its server processor roadmap through 2030 while outlining annual Instinct accelerator updates through 2028. Presented at the end of Advancing AI 2026, the schedule introduces several CPU, accelerator, networking and rack-system codenames that will follow the current EPYC Venice and Instinct MI400 generation. The seventh-generation EPYC family is scheduled for 2028 and will use Zen 7 and Zen 7c CPU cores. AMD identifies Florence as the primary processor family, accompanied by products or platform configurations named Ferrara and Fidenza. The company has not disclosed core counts, clock speeds, cache capacities or power limits. Zen 7 will be manufactured on what AMD currently describes as a next-generation process node. Earlier reports have associated the architecture with TSMC's A14, or 1.4 nm-class, technology, but AMD has not confirmed the foundry process. The roadmap instead focuses on architectural and platform additions, including a new matrix engine, more AI data formats and ACE extensions. Memory support will also move beyond the technologies used by current EPYC platforms. AMD lists next-generation MRDIMMs and low-power DDR among the planned additions. The presentation did not specify final memory standards, transfer rates, channel counts or capacity limits. These changes are intended to provide more bandwidth for AI and high-performance computing workloads, where data movement can limit the utilization of large CPU and accelerator configurations. AMD's CPU schedule continues into 2030 with Ravenna, the first officially named Zen 8-based EPYC generation. Ravenna is confirmed as being in development, but the company has not disclosed its process node, platform, core configuration or architectural features. The accelerator schedule will move more quickly. Instinct MI500 is planned for 2027 and will introduce new compute, memory and interconnect technologies. AMD's roadmap includes HBM4E memory alongside new copper and optical connections. These interconnect options will support scale-up communication inside systems and scale-out links between larger groups of AI hardware. MI500 will be integrated into Helios 500, AMD's 2027 rack-scale platform. Helios 500 combines MI500 accelerators with EPYC Verano processors and Pensando Como and Monza networking components. The following Helios 600 platform is planned for 2028 with Instinct MI600 GPUs, EPYC Ferrara processors and Pensando Palma and Levanzo networking. AMD has confirmed the MI600 name and launch year but has not yet published its GPU architecture, manufacturing process, HBM configuration or performance specifications. Reports assigning a specific CDNA generation to MI600 therefore remain speculative. Although the EPYC roadmap provides clues about future Ryzen technology, it does not confirm consumer CPU release dates. Zen architectures are normally adapted for both server and client products, but the named Florence, Ferrara, Fidenza and Ravenna families concern EPYC. Likewise, Instinct MI500 and MI600 are compute accelerators rather than Radeon gaming products, so their release schedule should not be interpreted as AMD's consumer GPU roadmap. Year Product or Codename Category Architecture or Role Confirmed Technologies 2027 Instinct MI500 Data-center accelerator Next-generation Instinct GPU HBM4E, new copper and optical interconnects 2027 Helios 500 Rack-scale AI platform MI500 GPUs and EPYC Verano CPUs Pensando Como and Monza networking 2028 Florence EPYC processor Zen 7 and Zen 7c Next-generation node, matrix engine and new AI formats 2028 Ferrara EPYC/AI infrastructure processor Zen 7 generation Used by the Helios 600 platform 2028 Fidenza EPYC/AI infrastructure product Zen 7 generation Specialized AI infrastructure role 2028 Instinct MI600 Data-center accelerator Architecture not disclosed Specifications not yet announced 2028 Helios 600 Rack-scale AI platform MI600 GPUs and EPYC Ferrara CPUs Pensando Palma and Levanzo networking 2030 Ravenna EPYC processor Zen 8 Technical details not yet disclosed Source: AMD

AMD announces 6th Gen AMD EPYC 'Venice' CPUs, up to 256 cores and 512 threads and built for AI

At AMD's Advancing AI 2026 event, the company formally lifted the lid on its 6th Gen AMD EPYC series of processors with the new 'Venice'-powered AMD EPYC 9006 Series. With multiple purpose-built models, AMD notes that the lineup is built for agentic AI, cloud computing, HPC, and general process workloads. Of course, it's the agentic AI focus that makes the 6th Gen AMD EPYC server CPUs stand out. That, and the impressive Compute configuration that features up to 256 Zen 6c cores, up to 96 Zen 6 cores, and 1152 MB of 3D V-Cache. "Agentic AI is reshaping how enterprise infrastructure is used and designed," AMD confirms. "It is transforming AI from systems that simply answer questions into systems that act, plan, call tools, write and execute code, and reason over enterprise data. Agentic AI depends on CPU-powered infrastructure to run agents, coordinate work around the model, connect to enterprise data and services, and keep accelerators fed across increasingly complex AI systems." As part of the announcement, AMD says that its 6th Gen AMD EPYC 'Venice' CPU lineup represents the world's best CPUs for cloud, enterprise, and AI, and the lineup is as broad as it is purpose-built. The AMD EPYC 9006 SP7 is tailor-made for agentic AI, featuring up to 256 cores and 512 threads, with up to 5 GHz of high-frequency performance. It also improves I/O with up to 128 lanes of PCIe Gen6 at 64 Gbps, plus 5th-Gen Infinity Fabric for CPU-to-GPU improvements that AMD says enable it to deliver more agents per watt, per dollar, and per rack than the competition. The AMD EPYC 9006X SP7 variant triples the L3 cache per core, while also boosting the frequency to 5.15 GHz and ramping up memory bandwidth for more data-intensive HPC workloads. On the other hand, the AMD EPYC 9006 SP8 is built for efficient agentic AI and enterprise, with a flexible 8- to 128-core design for power-constrained racks and edge computing. Rounding out the lineup, you've got the AMD EPYC 9006 LP, aka 'Verano', for rack-scale AI solutions with up to 72 cores, LPDDR5X memory support, and 112 Gbps CPU-to-GPU bandwidth. And with all of that, AMD notes that throughput and per-core performance leave NVIDIA's new 88-core Vera CPU in its wake, with 2.2X the throughput when looking at the 256-core variant, and 1.2X the per-core performance when comparing the 96-core AMD EPYC 9006X SP7 to Vera.

AMD EPYC 9006 (Venice) Server CPUs Announced - Scale to 256 Zen 6 Cores

AMD has formally detailed the sixth-generation EPYC 9006 server processor portfolio at Advancing AI 2026. The range includes models for dense CPU computing, general enterprise servers, high-performance computing and host nodes used in GPU-accelerated AI systems. At the top of the portfolio is the EPYC 9006 SP7 platform, offering configurations with as many as 256 cores and 512 threads. AMD expects the highest-core-count models to be used for densely consolidated services, virtual machines, containers and isolated environments in which AI agents can execute code and coordinate tasks. Selected SP7 models will operate at frequencies of up to 5 GHz. These higher-frequency versions can also function as host processors in GPU servers, where rapid data handling, I/O performance and CPU-to-accelerator communication are more important than using the maximum available core count. EPYC 9006 SP7 introduces PCI Express 6.0 and supports up to 16 memory channels. AMD lists MRDIMM transfer rates of up to 12.8 GT/s, providing additional memory bandwidth for systems containing multiple GPUs, network interfaces and storage controllers. The company has not yet supplied complete lane counts or detailed specifications for every model. EPYC 9006 SP8 addresses a broader range of conventional and power-sensitive systems. Core counts extend from 8 to 128, allowing the processors to be used in enterprise servers, edge locations, smaller clusters and racks with limited cooling or electrical capacity. SP8 is therefore positioned as a right-sized alternative to the denser SP7 platform. The EPYC 9006X SP7 family is intended for HPC and memory-sensitive applications. AMD says these processors provide three times the L3 cache per core of standard 9006 SP7 models. Selected versions reach frequencies of up to 5.15 GHz. Simulation, modelling, retrieval, analytics and in-memory processing are among the workloads expected to benefit from the larger cache. AMD has also disclosed EPYC 9006 LP, previously known as Verano. Unlike the regular SP7 and SP8 products, this processor is being designed primarily as a CPU host for dense accelerator racks. It uses LPDDR memory, reaches frequencies of up to 5 GHz and is intended to keep GPUs supplied with data as installations scale from individual servers to complete rack-scale AI platforms. The company describes these products as serving three CPU-dependent parts of an agent-based AI environment. CPUs execute and coordinate the agents, host processors manage data movement around GPU accelerators, and general-purpose processors continue to operate the databases, storage and enterprise applications used by those agents. AMD is also replacing its historical TDP terminology with Default CPU Power for sixth-generation EPYC. This measurement includes power consumed by both compute and I/O dies at the stated performance target. Exact model specifications, prices, release dates and power ratings remain to be announced. AMD's efficiency and agent-density comparisons are based on internal estimates and have not yet been independently verified. Processor family Platform Core range Maximum frequency Primary workloads Key characteristics AMD EPYC 9006 SP7 SP7 Up to 256 cores / 512 threads Up to 5.00 GHz Agent execution, dense computing and AI host nodes PCIe 6.0, up to 16 memory channels and MRDIMM support up to 12.8 GT/s AMD EPYC 9006 SP8 SP8 8 to 128 cores Not specified Enterprise servers, edge systems, smaller clusters and power-limited racks Smaller and lower-power configurations AMD EPYC 9006X SP7 SP7 Not specified Up to 5.15 GHz HPC, simulation, modelling, retrieval and analytics Up to three times the L3 cache per core of standard EPYC 9006 SP7 AMD EPYC 9006 LP Low-power AI host platform Not specified Up to 5.00 GHz Rack-scale AI host nodes LPDDR memory and accelerator-focused CPU communication

AMD's 256-core EPYC Venice die shot has been spotted on Moscone Center banners ahead of Lisa Su's keynote

Ahead of CEO Lisa Su's Advancing AI 2026 keynote in San Francisco, AMD has begun showcasing its upcoming EPYC Venice processor. Banners installed around the Moscone Center West, photographed by ComputerBase, include a detailed rendering of the flagship 256-core Venice chip's internal layout, and it is a genuinely impressive piece of silicon. The die shot confirms the structure AMD teased at CES earlier this year. Eight compute dies surround two large I/O dies at the center. Each compute die is a CCD containing two 16-core Core Complexes, giving each CCD 32 cores. Eight CCDs across 16 CCXs add up to 256 cores and 512 threads in the flagship configuration. The rendering shows cores arranged in a 2x4x4 layout within each CCD, consistent with the dense Zen 6c configuration used in the highest core count Venice processors rather than the larger standard Zen 6 cores. Venice is the first high-performance computing product to enter volume production on TSMC's 2nm process, which transitions from FinFET to Nanosheet transistors and delivers 10 to 15% higher performance at the same power, 25 to 30% lower power consumption at the same performance, and up to 15% higher transistor density. AMD has promised more than 70% performance and efficiency improvement over its current generation EPYC Turin chips, alongside a more than 30% increase in thread density. Agentic AI and reinforcement learning workloads are driving demand for high core count, high throughput server CPUs in a way that is pulling investment toward that space alongside GPUs. NVIDIA's Vera CPU is AMD's primary competitor here, and AMD has shown early benchmarks placing Venice well ahead. More details are expected during Lisa Su's keynote, where AMD is also expected to address its Helios rack-scale AI platform.

AMD EPYC Venice CPUs Stomp NVIDIA's Vera With 20% Faster Single-Core & 2.2x Higher Throughput With Up to 256 "Zen 6" Cores, 203 Billion Transistors & Over 5 GHz+ Clocks

AMD has officially launched its EPYC Venice CPU family, spanning several chips, with performance leadership in Agentic AI with Zen 6 cores. The Industry's First 2nm HPC CPU Is Here, Meet EPYC Venice Family, Packing Up To 256 "Zen 6" Cores & 203 Billion Transistors One component that is really shaping up as the king of the Agentic AI era is the CPU. AMD is leveraging its brand new Zen 6 core architecture that will be used on its 6th Gen EPYC CPUs, codenamed Venice. AMD's EPYC Venice chips are the first HPC product to enter volume production on TSMC's 2nm process technology, and their readiness for Helios AI racks proves that AMD will always deliver the best of the best for its high-performance customers. The TSMC 2nm process technology transitions from FinFET to Nanosheet transistors (GAA), and offers 10-15% higher performance at the same power, 25-30% lower power consumption at the same performance, and up to 15% higher transistor density. The EPYC Venice CPUs pack up to an insane 203 Billion Transistors while leveraging the 2nm process for the compute chiplet, and 6nm for the IO dies. AMD's 6th Gen EPYC Venice CPUs were teased earlier this year at CES, offering up to 256 cores and 512 threads with eight massive compute dies and two even larger I/O dies. For this chip, AMD has promised over 80% performance & efficiency improvement with its EPYC Venice CPUs, with a >30% increase in thread density. * Venice HF - Highest Performing CPU / 8 Compute Chips / 12 Zen 6 Cores / 5 GHz * Venice 256 - Agentic Sandboxes / 8 Compute Chips / 32 Zen 6C Cores * Venice 128 - Enterprise GPurpose Servers / Lower Power Design Once again, the requirement for high-performance CPUs has risen tenfold with Agentic AI workloads. And competitors are firing across all cylinders with CPUs that are optimized around agents. Just like GPUs, NVIDIA is AMD's primary competitor in this space, which is leveraging Vera CPUs based on its custom Arm IP to power the Vera Rubin NVL72 racks. AMD's Helios AI racks powered by Zen 6 EPYC chips not only offer more cores, but faster performance and improved single-core capabilities, which is important for sustained throughput. In benchmarks, AMD has shown that not only do its 5th Gen Turin "Zen 5" CPUs lead against Vera, but the 6th Gen Venice "Zen 6" chips lead massively, driving more performance & offering better TCOs at a similar power scale. For example, in Agentic CPU servers "sandboxes", AMD is claiming up to 2.8x agents per watt versus Arm-based CPUs such as NVIDIA's Vera, and up to 3.3x performance per watt in General-Purpose CPU servers. AMD is also bringing up to 1.8x tokens/s, 1.7x agents/watt, and 1.4x performance/watt versus its 5th Gen EPYC "Turin" CPUs. AMD EPYC CPU Families: Follow Wccftech on Google to get more of our news coverage in your feeds.

AMD EPYC Verano "Highest Frequency" & Venice-X "3D V-Cache" CPUs Launch Next Year, Tackling Agentic AI & HPC-Oriented Workloads With Zen 6

AMD has confirmed that its EPYC Verano and 3D V-Cache boosted Venice-X CPUs will launch next year as Zen 6 tackles a broad range of HPC & AI workloads. AMD Verano Couples High-Frequency Zen 6 With Efficiency-Optimized LPDDR Memory While Venice-X Tackles HPC With 3D V-Cache Boost Today at Advancing AI 2026, AMD confirmed that its EPYC CPU lineup will be expanded next year with even more options aimed at AI and HPC workloads. The two brand new chips for 2027 are EPYC Verano and EPYC Venice-X. Microsoft already spilled the beans on the AMD Venice-X chips, which will be deployed within its Azure HXv2 instances next year. The chips will feature 176 "Zen 6" cores, 342 threads, over 5 GHz clock speeds, and 50% more addressable cache per core as the 3D V-Cache stacks sit beneath the Zen 6 cores to offer increased technical compute and HPC capabilities. Verano Is Purpose-Built For Agents AMD's EPYC Verano CPUs will be the first to support SOCAMM2 memory. SOCAMM2 is a relatively new memory form factor that currently harnesses LPDDR5X DRAM modules and offers high bandwidth, high capacity, and much better power efficiency in a compact form factor. This allows tech vendors to ensure maximum memory density. For example, Micron recently shipped SOCAMM2 modules to various partners working on infrastructure for AI. These modules house 256 GB densities and are specifically targeted towards AI at scale. NVIDIA's Vera CPU solution features 16 of these modules with four LPDDR5X modules each for a total of 64 DRAM packages. CPU for future generations of AMD Instinct accelerators, such as the MI500 series we mentioned above. Now here's the interesting bit: AMD isn't the only one that will be using SOCAMM2 memory. Like AMD, NVIDIA's next-gen Vera Rubin and Vera CPX platforms also feature SOCAMM2 LPDDR5X memory. And LPDDR is also the prime choice of several upcoming AI accelerators, such as Tesla's A15, which was recently revealed, and also several Intel inference-optimized GPU solutions. This worsens the already-worse situation for LPDDR since the overall memory supply chain is tight, and the constraints aren't seeing any sign of relief. With more dense solutions rolling out in the future, it is not only going to affect server and PC audiences, but low-power DDR memory is also a vital component for smartphones, and with a large supply heading to AI racks, this could further disrupt the tech industry as a whole. AMD EPYC CPU Families: Follow Wccftech on Google to get more of our news coverage in your feeds.

AMD's Zen 6 EPYC Venice Pictured as a 256-Core Monster, Massive Twin I/O Dies & First 2nm HPC Chip To Enter Volume Ramp

AMD has showcased its next-generation EPYC Venice CPU at the Advancing AI event, featuring a phenomenal core count of 256 based on Zen 6. AMD Is Firing Across All Cylinders With Its Next-Gen EPYC Venice CPU Lineup: Flagship With 256 "Zen 6" Cores Pictured & It's A Monster Chip For the next stream of data centers, CPUs are going to play a much more important role than GPUs due to the rise in Agentic AI & RL workflows. As such, all CPU vendors are releasing brand new chips that unleash the best capabilities for these workloads while leading the charts against the competition. At Advancing AI 2026, AMD has confirmed to launch its EPYC Venice CPUs based on the Zen 6 core architecture. But while there are still a few hours left in the official presentation, the company has set banners across the Moscone Center West in San Francisco, US. One of these banners featured a very peculiar-looking chip as spotted by Computerbase, and it turns out to be none other than the flagship 256-core EPYC champion. AMD is leveraging its brand new Zen 6 core architecture that will be used on its 6th Gen EPYC CPUs, codenamed Venice. AMD's EPYC Venice chips are the first HPC product to enter volume production on TSMC's 2nm process technology, and their readiness for Helios AI racks proves that AMD will always deliver the best of the best for its high-performance customers. The TSMC 2nm process technology transitions from FinFET to Nanosheet transistors (GAA), and offers 10-15% higher performance at the same power, 25-30% lower power consumption at the same performance, and up to 15% higher transistor density. AMD's 6th Gen EPYC Venice CPUs were teased earlier this year at CES, offering up to 256 cores and 512 threads with eight massive compute dies and two even larger I/O dies. You can also see that each of the eight massive CCDs features a total of 32 cores, sliced into two 16-core complexes. The IO chips in the middle look massive in size, with lots of controllers such as PCIe 6.0, UCIe, DDR5, and more. For this chip, AMD has promised over 70% performance & efficiency improvement with its EPYC Venice CPUs, with a >30% increase in thread density. Once again, the requirement for high-performance CPUs has risen tenfold with Agentic AI workloads. And competitors are firing across all cylinders with CPUs that are optimized around agents. Just like GPUs, NVIDIA is AMD's primary competitor in this space, which is leveraging Vera CPUs based on its custom Arm IP to power the Vera Rubin NVL72 racks. AMD's Helios AI racks powered by Zen 6 EPYC chips not only offer more cores, but faster performance and improved single-core capabilities, which is important for sustained throughput. In early benchmarks, AMD has shown that not only do its 5th Gen Turin "Zen 5" CPUs lead against Vera, but the 6th Gen Venice "Zen 6" chips lead massively, driving more performance & offering better TCOs at a similar power scale. AMD EPYC CPU Families: Follow Wccftech on Google to get more of our news coverage in your feeds.