AMD splits Zen 7 into three EPYC families for 2028 as it pushes deeper into AI server market
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AMD splits Zen 7 into three EPYC families for 2028 and starts selling server CPUs by the agent -- Florence, Ferrara, and Fidenza to be applied across AI-focused product stack
AMD used its recent Advancing AI 2026 event in San Francisco to launch sixth-gen EPYC "Venice" processors, Instinct MI400 Series GPUs, and Helios rack-scale systems, and to confirm that the Zen 7 generation arriving in 2028 will launch as three separate EPYC families rather than one. The company
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AMD EPYC 9006 Venice Announced & Looks Poised To Be A Grand Slam
While AMD EPYC 9005 "Turin" launched just under two years ago, it has aged remarkably well. It is one of the few CPU generations in my past 22 years of Linux hardware reviews/benchmarking that has still captivated me two years on in finding still typically industry-leading performance across
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AMD's 6th Gen EPYC lineup splits four ways -- and the power spec changed, too
His love of PCs and their components was born out of trying to squeeze every ounce of performance out of the family computer. Tinkering with his own build at age 10 turned into building PCs for friends and family, fostering a passion that would ultimately take shape as a career path. Besides being
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AMD confirms Zen 7 Epyc "Florence" for 2028 and previews Zen 8 Epyc "Ravenna" for 2030
Serving tech enthusiasts for over 25 years. TechSpot means tech analysis and advice you can trust. The big picture: AMD had a busy week, announcing the Ryzen 7 7700X3D CPU for gaming PCs and the Epyc Venice lineup for agentic AI workloads in data centers and high-end workstations. The company
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AMD's Venice is the first 2nm x86 server chip, but the stack doesn't fully ship until 2027
* AMD EPYC 9006 "Venice" offers mammoth 256-core, 512-thread configuration that incorporates up to 1GB of L3 cache and PCI-E 6.0 and 16 DDR5 memory channels under the hood * It's the first time AMD's EPYC lineup sees high core count CPUs push past the 5GHz barrier * AMD is claiming a win by
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AMD Maps EPYC and Instinct Generations Through 2030 With Zen 8
AMD has extended its server processor roadmap through 2030 while outlining annual Instinct accelerator updates through 2028. Presented at the end of Advancing AI 2026, the schedule introduces several CPU, accelerator, networking and rack-system codenames that will follow the current EPYC Venice and
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AMD announces 6th Gen AMD EPYC 'Venice' CPUs, up to 256 cores and 512 threads and built for AI
At AMD's Advancing AI 2026 event, the company formally lifted the lid on its 6th Gen AMD EPYC series of processors with the new 'Venice'-powered AMD EPYC 9006 Series. With multiple purpose-built models, AMD notes that the lineup is built for agentic AI, cloud computing, HPC, and general process
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AMD EPYC 9006 (Venice) Server CPUs Announced - Scale to 256 Zen 6 Cores
AMD has formally detailed the sixth-generation EPYC 9006 server processor portfolio at Advancing AI 2026. The range includes models for dense CPU computing, general enterprise servers, high-performance computing and host nodes used in GPU-accelerated AI systems. At the top of the portfolio is the
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AMD's 256-core EPYC Venice die shot has been spotted on Moscone Center banners ahead of Lisa Su's keynote
Ahead of CEO Lisa Su's Advancing AI 2026 keynote in San Francisco, AMD has begun showcasing its upcoming EPYC Venice processor. Banners installed around the Moscone Center West, photographed by ComputerBase, include a detailed rendering of the flagship 256-core Venice chip's internal layout, and it
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AMD EPYC Venice CPUs Stomp NVIDIA's Vera With 20% Faster Single-Core & 2.2x Higher Throughput With Up to 256 "Zen 6" Cores, 203 Billion Transistors & Over 5 GHz+ Clocks
AMD has officially launched its EPYC Venice CPU family, spanning several chips, with performance leadership in Agentic AI with Zen 6 cores. The Industry's First 2nm HPC CPU Is Here, Meet EPYC Venice Family, Packing Up To 256 "Zen 6" Cores & 203 Billion Transistors One component that is really
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AMD EPYC Verano "Highest Frequency" & Venice-X "3D V-Cache" CPUs Launch Next Year, Tackling Agentic AI & HPC-Oriented Workloads With Zen 6
AMD has confirmed that its EPYC Verano and 3D V-Cache boosted Venice-X CPUs will launch next year as Zen 6 tackles a broad range of HPC & AI workloads. AMD Verano Couples High-Frequency Zen 6 With Efficiency-Optimized LPDDR Memory While Venice-X Tackles HPC With 3D V-Cache Boost Today at
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AMD's Zen 6 EPYC Venice Pictured as a 256-Core Monster, Massive Twin I/O Dies & First 2nm HPC Chip To Enter Volume Ramp
AMD has showcased its next-generation EPYC Venice CPU at the Advancing AI event, featuring a phenomenal core count of 256 based on Zen 6. AMD Is Firing Across All Cylinders With Its Next-Gen EPYC Venice CPU Lineup: Flagship With 256 "Zen 6" Cores Pictured & It's A Monster Chip For the next stream
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AMD announced its 6th Gen EPYC Venice processors at the Advancing AI 2026 event, revealing plans to split Zen 7 into three distinct EPYC families—Florence, Ferrara, and Fidenza—arriving in 2028. The Venice lineup features up to 256 cores and 512 threads, built on TSMC's 2nm process node, with support for PCIe Gen 6 and DDR5-8000 memory. AMD also extended its roadmap to 2030 with Zen 8 Ravenna.
AMD EPYC Venice Launches as Gateway to Three-Family Zen 7 Strategy
AMD used its Advancing AI 2026 event in San Francisco to announce 6th Gen EPYC Venice server processors while confirming an unprecedented split of its upcoming Zen 7 architecture into three distinct EPYC families for 2028. The company named Florence, Ferrara, and Fidenza as separate product lines, marking the widest architectural spread AMD has ever opened a generation with
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. CEO Lisa Su revealed that Florence will carry fresh Zen 7 cores, new AI compute extensions, and support for next-generation memory technologies, while Ferrara targets AI host node deployments and Fidenza focuses on agentic sandbox workloads1
. AMD disclosed no core counts, process node details, or socket information for the Zen 7 EPYC families, stating only that they will use leading-edge process technology4
. The company also previewed Zen 8 with EPYC Ravenna slated for 2030, extending its annual CPU, GPU, networking, and rack cadence while putting its total addressable market at roughly $2 trillion in 20301
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Source: XDA-Developers
EPYC 9006 Venice Delivers 256 Cores on 2nm Process Node
The EPYC 9006 Venice represents AMD's first x86 server chip built on a 2nm-class process node, specifically TSMC's N2 technology featuring gate-all-around nanosheet transistors
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. The flagship 256-core, 512-thread EPYC 9996 configuration incorporates up to 1GB of L3 cache and marks the first time AMD's high core count server processors push past the 5GHz barrier5
. Venice supports 16-channel memory per socket with DDR5-8000 and MRDIMM-12800 MT/s speeds, delivering roughly 1.6 TB/s per socket and eliminating Intel Xeon 6 Granite Rapids' previous memory bandwidth advantage2
. The processors also feature PCIe Gen 6 support with up to 160 lanes in dual socket configurations2
. AMD improved its AVX-512 support with AVX-512 BMM extensions, positioning Venice to deliver approximately 20% more performance per core compared to the already strong EPYC 9005 Turin generation2
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Source: TweakTown
Four Distinct Families Target Different AI Data Center CPUs Segments
AMD divided the 6th Gen EPYC lineup into four families, each matched to specific jobs in the data center
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. The EPYC 9006 SP7 anchors the top with up to 256 cores for high-density agent sandbox execution, while the 9006X SP7 targets HPC and technical computing with three times the L3 cache per core and boost clocks reaching 5.15GHz3
. The 9006 SP8 covers right-sized deployments with 8- to 128-core options for edge sites and power-constrained racks, and the 9006 LP (codenamed Verano) serves as a purpose-built AI host node CPU using LPDDR memory3
. The flagship 9006 SP7 enters production in Q4 2026, while the complete stack won't fully ship until 20275
. AMD argues that data centers are evolving into a three-tier agentic architecture, with each tier creating distinct CPU demand around agent sandbox execution, AI host nodes, and general-purpose servers5
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Helios Rack-Scale Systems Integrate Venice with Instinct MI455X
AMD launched Helios rack-scale systems pairing 72 Instinct MI455X GPUs with 18 Venice CPUs, 31TB of HBM4, and 1.4 PB/s of aggregate memory bandwidth, with production already underway
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. The company claims up to 30% more inference tokens per dollar than Nvidia Vera Rubin NVL72, based on AMD Performance Labs estimates using a Kimi K2 Thinking workload at 32K input and 8K output1
. OpenAI expects to bring Helios online from Q4 2026, with deployments accelerating thereafter1
. The forward roadmap extends through Helios 500 in 2027 with MI500 GPUs and EPYC Verano, followed by Helios 600 in 2028 featuring MI600 accelerators and Ferrara processors1
. AMD introduced a competitive metric claiming the most AI agents per watt, per dollar, and per rack, though endnotes reveal agent counts are estimates derived from CPU thread resources used as a proxy1
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Source: Guru3D
Power Metric Shift and Competitive Positioning in Agentic AI Era
Starting with 6th Gen EPYC, AMD replaced TDP with Default CPU Power, defined as total power consumed across the processor's compute and I/O dies at a stated performance target
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. The company's footnotes list the EPYC 9956 at 400W Default CPU Power compared to the previous-generation 9965 at 500W TDP, though AMD states both references can serve for product comparison and power efficiency analysis3
. Mercury Research placed AMD at a record 46.2% of x86 server CPU revenue in Q1 2026 against 33.2% of units, while Arm-based designs took roughly 17.7% of server shipments in the same quarter1
. AMD's widening comparisons against Nvidia Vera, Intel Xeon 6980P, and Arm's AGI CPU demonstrate where these AI workloads are heading as the industry enters what AMD calls the agentic AI era2
. With Intel's Diamond Rapids competition not arriving until at least 2027, AMD appears positioned to maintain its server market momentum through the transition to Florence and beyond2
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