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Broadcom teases 'cutting-edge' 3.5D XDSiP tech: 4 compute tiles, 12 HBM sites fabbed by TSMC
TL;DR: Broadcom has introduced its 3.5D eXtreme Dimension System in Package (XDSiP) technology, enabling AI customers to develop advanced custom accelerators. This platform integrates over 6000 mm² of silicon and up to 12 HBM stacks, enhancing efficiency and reducing power consumption. It combines
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Broadcom Unveils "Cutting-Edge" 3.5D XDSiP Technology, Embeds Four Compute Tiles & 12 HBM Sites On A Single Package
Broadcom has unveiled its "cutting-edge" 3.5D XDSiP platform technology, focused on custom compute platforms to bring in significant performance and efficiency gains. Broadcom's Newest 3.5D XDSiP Platform Brings In Enablement For Large-Scale AI XPU, Focusing On AI & HPC Workloads [Press Release]:
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Broadcom introduces its 3.5D eXtreme Dimension System in Package (XDSiP) technology, enabling the development of advanced custom AI accelerators with improved efficiency and performance.

Broadcom has unveiled its groundbreaking 3.5D eXtreme Dimension System in Package (XDSiP) platform technology, aimed at revolutionizing the development of next-generation custom AI accelerators (XPUs). This innovative technology addresses the growing demands of generative AI models by integrating over 6000 mm² of silicon and up to 12 high bandwidth memory (HBM) stacks in a single package
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.As the computational requirements for training generative AI models continue to escalate, traditional methods like Moore's Law and process scaling are struggling to keep pace. Broadcom's 3.5D XDSiP technology emerges as a crucial solution, combining 3D silicon stacking with 2.5D packaging to achieve significant improvements in performance, efficiency, and cost
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.The 3.5D XDSiP platform introduces several groundbreaking features:
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Broadcom's 3.5D XDSiP technology leverages TSMC's cutting-edge process nodes and 2.5D CoWoS packaging technologies. This collaboration brings together TSMC's advanced logic processes and 3D chip stacking technologies with Broadcom's design expertise
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.Frank Ostojic, Senior Vice President and General Manager of Broadcom's ASIC Products Division, emphasizes the critical role of advanced packaging in next-generation XPU clusters. The 3.5D platform enables chip designers to optimize fabrication processes for each component while reducing interposer and package size
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.With more than five 3.5D products in development, a majority of Broadcom's consumer AI customers have already adopted the 3.5D XDSiP platform technology. Production shipments are scheduled to begin in February 2026, signaling a new era in AI accelerator design and performance
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.As the demand for AI computing power continues to grow, Broadcom's 3.5D XDSiP technology is poised to play a crucial role in shaping the future of AI hardware, enabling more efficient and powerful systems for training and deploying complex AI models.
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