Celero Communications Secures $275M at $3B Valuation for AI Infrastructure Chips

Celero Communications Closes $275M Series C at $3B Valuation

Celero Communications announced it has raised $275 million in Series C funding, valuing the data center networking chips startup at $3 billion1

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. The round was led by Alphabet's CapitalG fund, Atreides Management and Valor Equity Partners, with participation from returning backers Sutter Hill Ventures and Maverick Silicon1

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. The Irvine, California-based company has now raised $415 million in total capital since its founding in 20242

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. Gavin Baker, Managing Partner and Chief Investment Officer at Atreides Management, will join Celero's board of directors as part of the financing2

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Coherent DSP Technology Addresses Critical AI Infrastructure Bottleneck

Celero specializes in developing coherent digital signal processors specifically optimized for AI workloads1

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. These chips manage transceivers in data center networks, converting digital data stored as electricity into light that travels over fiber-optic cables spanning more than 100 miles between facilities1

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. The company's technology provides lower latency than current chips and uses less power, addressing a critical need as AI infrastructure scales1

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. Coherent DSPs play an essential role in maintaining network reliability by addressing data loss that occurs when light disperses and dims inside fiber-optic cables, extending data streams with extra bits that enable recipients to fix transmission errors1

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Industry-First 2nm Coherent DSP Silicon Validation

Ahead of the funding announcement, Celero achieved a significant milestone by validating the industry's first 2nm coherent DSP silicon, including DSP processing and advanced analog technology2

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. The chip can be manufactured using Taiwan Semiconductor Manufacturing Co.'s two-nanometer node, the most advanced semiconductor production technology on the market, which provides 15% better performance than its predecessor1

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. Celero's two-nanometer design can support 1.6T and 3.2T interconnects, transmitting up to 3.2 terabits per second per port—significantly faster than today's AI networks1

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. This establishes a foundation for next-generation AI networks and AI optical interconnects as hyperscale AI clusters and cloud data centers scale2

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Addressing Scale-Out Networking and Multi-Trillion Dollar Market Opportunity

Celero's coherent DSP can power not only long-haul links between data centers but also their internal networks, supporting both scale-up and scale-out networking1

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. Scale-up networking connects chips in the same rack, while scale-out networking links together different racks1

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. The market opportunity is substantial: global data centers are projected to require nearly $7 trillion in investment by 2030, including approximately $5.2 trillion to support AI workloads, according to McKinsey & Company2

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. Connectivity is becoming a critical bottleneck as AI infrastructure scales, pushing traditional PAM4 optical architectures toward their practical limits in bandwidth density and fiber scalability2

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Product Development and Manufacturing Roadmap Acceleration

Celero will deploy the Series C funding to accelerate its product development roadmap, R&D investments and production readiness as AI chip demand grows for high-bandwidth low-power optical connectivity across next-generation AI infrastructure1

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. "AI infrastructure is rapidly outgrowing the capabilities of traditional optical interconnect architectures," said Celero co-founder and Chief Executive Officer Nariman Yousefi. "Our 2nm silicon validation demonstrates that coherent technology can deliver the bandwidth density, power efficiency and scalability required for the next generation of AI networks"1

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. The company was founded by industry leaders from Marvell, Inphi, Broadcom and ClariPhy, with design centers in Canada and Argentina2

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. Watch for Celero's product launches as hyperscalers race to build out AI infrastructure capable of supporting increasingly demanding workloads.