Google Teams with AMD on 10th-Generation TPU Project for Reinforcement Learning Workloads

Google Explores Hybrid AI Architecture with AMD Partnership

Google is working with AMD on a 10th-generation TPU project, according to semiconductor research firm SemiAnalysis1

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. This collaboration would mark AMD's first major involvement in a custom AI accelerator project and signals a potential shift in how Google approaches AI hardware innovation. Market chatter suggests Google is exploring a hybrid AI ASIC design that combines its proprietary Tensor Processing Unit technology with on-package CPU cores, a departure from conventional accelerator-heavy designs1

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Why AMD's CPU Expertise Matters for Next-Generation TPUs

Google has developed nine generations of TPUs with Broadcom as the primary silicon designer and maintains a long-term supply agreement running through at least 20312

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. Given Google's extensive expertise in accelerator architecture, analysts believe the company needs something only a CPU maker like AMD could provide. SemiAnalysis points to AMD's strong intellectual property portfolio, particularly in advanced packaging and CPU cores, as key attractions1

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. AMD already has experience building hybrid designs through its Instinct MI300A, which packs both x86 and accelerator chiplets in a single package1

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Reinforcement Learning Drives Demand for CPU-Heavy Tasks

The reported collaboration stems from Google and its customers pushing for TPUs with on-package CPU cores specifically for reinforcement learning and agentic AI workloads1

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. While conventional large language model training remains overwhelmingly accelerator-heavy, reinforcement learning for reasoning and agentic models requires considerably more general-purpose compute around accelerator operations1

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. Google has already begun increasing CPU resources in its latest systems. The TPU 8i systems pair one Google Axion CPU with every two TPUs, doubling the ratio used with seventh-generation hardware that deployed one Xeon Emerald Rapid processor for every four TPUs1

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Future AI Systems May Require 1:1 CPU-to-Accelerator Ratios

SemiAnalysis indicates that in some configurations, a 1:1 ratio of CPUs to accelerators may be optimal, suggesting the future of AI could be far more CPU-heavy than current architectures1

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. Bringing CPU cores directly into the TPU package represents a logical next step, as reducing the distance between general-purpose and tensor compute chiplets can improve performance and reduce power consumption1

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. A hypothetical Google design could combine Google-developed TPU compute chiplets with AMD CPU and HBM in a tightly integrated package built by AMD1

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. Neither Google nor AMD has publicly commented on the collaboration, and the scope of AMD's role remains unclear2

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. Watch for official announcements that could reshape expectations around AI infrastructure requirements and signal broader industry shifts toward hybrid compute architectures.