Spintronic computing hardware outpaces quantum annealers in speed and energy efficiency

Spintronic hardware unlocks faster, lower-energy optimization, outpacing tested quantum annealers

Solving complex optimization problems is central to many modern technologies, from logistics and financial modeling to chip design, communications and artificial intelligence (AI). However, as these problems grow in size, conventional computers often require substantial time and energy to search for good solutions. A research team led by Professor Yang Hyunsoo from the Department of Electrical and Computer Engineering in the College of Design and Engineering at the National University of Singapore (NUS) has developed new spintronic computing hardware that offers a promising route toward faster, more energy-efficient optimization. The team reported two recent advances in Nature Communications, demonstrating probabilistic computing systems based on magnetic tunnel junctions, nanoscale devices that can naturally generate tunable randomness. A practical path beyond conventional computing Quantum computing has long been viewed as a potential breakthrough for optimization, but practical quantum advantage remains difficult to achieve in the near term. The NUS team's work shows that probabilistic computing, built using scalable spintronic hardware, could provide a more immediate, hardware-efficient path. In the first study, the researchers demonstrated a parallel magnetic tunnel junction-based probabilistic Ising processor for solving quadratic assignment problems, a class of computationally demanding optimization problems. The system integrates 144 compact spintronic tunable random number generators in a massively parallel architecture. The processor achieved a 3.2-fold speedup with 58.3% energy savings compared with a central processing unit (CPU) implementation. Importantly, the team compared its system with state-of-the-art D-Wave quantum annealers. In the tested quadratic assignment problems, the spintronic probabilistic processor consistently produced feasible, high-quality solutions across the full data set, while the quantum annealers struggled to return feasible solutions as the problem size increased. This comparison highlights the potential of spintronic probabilistic computing as a practical near-term alternative for real-world optimization workloads. "Quantum computing remains an exciting long-term direction, but many optimization problems need practical solutions today," said Professor Yang. "Our results show that spintronic probabilistic computing can deliver strong gains in speed, energy efficiency and solution quality using a hardware platform that is much closer to practical deployment." In the second study, the team demonstrated a larger probabilistic Ising machine based on 250 spin-transfer-torque magnetic tunnel junctions. The work showed that a cluster parallel update method could achieve a 10-fold acceleration for sparsely connected graphs without changing the hardware. The researchers also experimentally showed that simulated quantum annealing improved solution quality by 20 times compared with conventional simulated annealing, while increasing robustness to device variability. "Instead of treating randomness as a source of error, we use it as a computing resource," said Yang Shuhan, a Ph.D. student in the College of Design and Engineering at NUS and the first author of both papers. "By combining stochastic magnetic devices with parallel architectures and advanced annealing algorithms, we can accelerate optimization while reducing energy consumption." Together, the two studies address key challenges in probabilistic computing: performance, scalability, energy efficiency and solution quality. The research involved collaborators from the Indian Institute of Technology Madras, Politecnico di Bari, the University of Messina, Istituto Nazionale di Geofisica e Vulcanologia and Peking University. Potential applications and next steps Looking ahead, the team aims to further scale up the hardware and explore chiplet-based architectures for large-scale probabilistic computing. Such systems could eventually support energy-efficient computing platforms for AI, logistics, scheduling, financial modeling, communications and electronic design automation.

NUS Researchers Develop Probabilistic Spintronic Processors for Faster and Greener Optimisation | Newswise

In a breakthrough for high-performance and energy-efficient computing, researchers have demonstrated novel spintronics-based probabilistic processors that accelerate complex optimisation tasks while consuming less energy, offering a practical near-term route for AI, logistics, chip design and other demanding applications Newswise -- Solving complex optimisation problems is central to many modern technologies, from logistics and financial modelling to chip design, communications and artificial intelligence (AI). However, as these problems grow in size, conventional computers often require substantial time and energy to search for good solutions. A research team led by Professor Yang Hyunsoo from the Department of Electrical and Computer Engineering in the College of Design and Engineering at the National University of Singapore (NUS) has developed new spintronic computing hardware that offers a promising route towards faster and more energy-efficient optimisation. The team reported two recent advances in Nature Communications, demonstrating probabilistic computing systems based on magnetic tunnel junctions, nanoscale devices that can naturally generate tuneable randomness. A practical path beyond conventional computing Quantum computing has long been viewed as a potential breakthrough for optimisation, but practical quantum advantage remains difficult to achieve in the near term. The NUS team's work shows that probabilistic computing, built using scalable spintronic hardware, could provide a more immediate and hardware-efficient path. In the first study, the researchers demonstrated a parallel magnetic tunnel junction-based probabilistic Ising processor for solving quadratic assignment problems, a class of computationally demanding optimisation problems. The system integrates 144 compact spintronic tuneable random number generators in a massively parallel architecture. The processor achieved a 3.2-fold speedup with 58.3 per cent energy savings compared with a central processing unit (CPU) implementation. Importantly, the team compared its system with state-of-the-art D-Wave quantum annealers. In the tested quadratic assignment problems, the spintronic probabilistic processor consistently produced feasible, high-quality solutions across the full dataset, while the quantum annealers struggled to return feasible solutions as the problem size increased. This comparison highlights the potential of spintronic probabilistic computing as a practical near-term alternative for real-world optimisation workloads. "Quantum computing remains an exciting long-term direction, but many optimisation problems need practical solutions today," said Prof Yang. "Our results show that spintronic probabilistic computing can deliver strong gains in speed, energy efficiency and solution quality using a hardware platform that is much closer to practical deployment." In the second study, the team demonstrated a larger probabilistic Ising machine based on 250 spin-transfer-torque magnetic tunnel junctions. The work showed that a cluster parallel update method could achieve a 10-fold acceleration for sparsely connected graphs without changing the hardware. The researchers also experimentally showed that simulated quantum annealing improved solution quality by 20 times compared to conventional simulated annealing, while increasing robustness to device variability. "Instead of treating randomness as a source of error, we use it as a computing resource," said Mr Yang Shuhan, PhD student in the College of Design and Engineering at NUS and the first author of both papers. "By combining stochastic magnetic devices with parallel architectures and advanced annealing algorithms, we can accelerate optimisation while reducing energy consumption." Together, the two studies address key challenges in probabilistic computing: performance, scalability, energy efficiency and solution quality. The research involved collaborators from the Indian Institute of Technology Madras, Politecnico di Bari, the University of Messina, Istituto Nazionale di Geofisica e Vulcanologia, and Peking University. Potential applications and next steps Looking ahead, the team aims to further scale up the hardware and explore chiplet-based architectures for large-scale probabilistic computing. Such systems could eventually support energy-efficient computing platforms for AI, logistics, scheduling, financial modelling, communications and electronic design automation.