TSMC targets 30% power savings as AI energy crisis forces chip design rethink

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TSMC says surging electricity demands from AI are making energy efficiency the main constraint shaping future chip development. The world's largest contract chipmaker expects to cut power consumption by up to 30% by 2028 while delivering over 20% higher computing performance, as customers from smartphones to AI data centers prioritize performance with lower power usage.

Energy Efficiency Now Drives AI Chip Design

The massive electricity demands of AI are fundamentally reshaping how the semiconductor industry approaches chip development. TSMC, the world's largest contract chipmaker, revealed that energy efficiency has overtaken raw computing power as the primary constraint driving future AI chip design decisions

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. Kevin Zhang, Senior Vice President of Business Development at TSMC, told reporters at a conference in Amsterdam that customers across smartphones, IoT devices, and AI data centers are increasingly prioritizing performance gains that do not drive up power use

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Source: ET

Source: ET

"The area customers most want improvement in is energy efficiency. This is true across the board, whether you are the edge guy, smartphone, mobile, IoT application, or high-performance AI data center," Zhang said

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. The shift marks a broader turning point for the semiconductor industry, where simply packing more transistors onto chips is no longer sufficient to sustain performance gains for energy-hungry AI workloads.

TSMC Sets Ambitious Targets for Cutting Power Consumption

TSMC expects its chips to cut power consumption by up to 30% between its current N2 technology and its A14 generation, due around 2028, while delivering more than 20% higher computing performance

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. This aggressive timeline reflects the urgency with which the AI energy crisis is forcing a rethink of AI chip design across the industry. The chipmaker, which manufactures AI chips for NVIDIA and AMD, as well as custom AI processors for major cloud companies including Google, Amazon, Meta, and Microsoft, sees this transition as essential to meeting customer demands

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Source: Benzinga

Source: Benzinga

Zhang emphasized that while improvements in transistor-density remain central to TSMC's roadmap, other approaches are becoming increasingly important to boost efficiency

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. Advanced packaging, chip stacking, and photonics are now critical technologies in achieving performance with lower power usage

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Industry-Wide Implications and Competitive Landscape

The focus on energy efficiency comes as operators contend with both the cost and availability of electricity for AI data centers. Rivals are also exploring alternative ways to keep improving chip performance. Chinese competitor Huawei unveiled its 'Tau Scaling Law' plan this week to improve performance by speeding up data movement within chips

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. Zhang described this concept as largely dependent on integrating components more closely, such as through 3D stacking

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Huawei's approach reflects constraints facing Chinese firms, which are barred by U.S.-led export controls from accessing extreme ultraviolet (EUV) lithography machines made by Dutch ASML

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. Meanwhile, U.S.-China chip policy continues to influence market sentiment, with mainland China accounting for 9% of TSMC's fiscal 2025 net revenue

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. TSMC said in April it would delay adoption for several years of the next generation of EUV technology, highlighting how design features improving energy efficiency are becoming more urgent than smaller circuitry for its coming generation of AI chips

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. TSMC shares were trading up 0.56% at $427.25 during premarket trading, near its 52-week high of $430.55, with analysts maintaining a Buy rating and an average price target of $420.00

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