AMD EPYC Venice enters production as first 2nm HPC chip with 256 cores and 70% performance leap

AMD begins production ramp of 256-core EPYC Venice -- first 2nm HPC chip claims 70% performance leap

Intel's competing P-core Xeon won't arrive until 2027 at the earliest. AMD has announced that its 6th Gen EPYC processor, codenamed Venice, has entered production ramp on TSMC's N2 (2nm-class) process technology in Taiwan. The chip, which packs up to 256 Zen 6 cores and claims a 70% compute performance gain over the current EPYC Turin lineup, is the first high-performance computing product in the industry to reach production on N2. AMD also announced a follow-on processor called Verano and said it plans to eventually produce Venice at TSMC's Arizona campus as well. TSMC began volume production on its N2 node late last year, and the foundry is ramping five separate 2nm fabs this year to meet what it has described as record demand. Apple reportedly secured the lion's share of initial N2 capacity for consumer silicon, but it's AMD with Venice that'll be the first HPC product on the node. Server and data center dies are larger and architecturally more complex than smartphone SoCs, and getting them through yield qualification on a brand-new process is a much bigger challenge. "As AI and agentic workloads scale rapidly, customers need platforms that can move from innovation to production faster," said Dr. Lisa Su, chair and CEO of AMD, in the company's press release. Venice brings the new SP7 socket, up to 16 memory channels delivering 1.6 TB/s of per-socket bandwidth, and doubled CPU-to-GPU bandwidth that likely indicates PCIe 6.0 support. AMD previewed these specs at its Advancing AI event last year and at CES in January, but this announcement puts the chip on track for commercial shipments later this year. AMD could face limited next-gen competition in the server market right now, with Intel's Diamond Rapids -- the P-core Xeon 7 family that would be Venice's direct counterpart -- rumored to be delayed to mid-2027. Intel's only new server product expected this year is Clearwater Forest, an E-core design built on Intel 18A with up to 288 cores. Clearwater Forest is optimized for high-density deployments at scale, not the high single-thread and general-purpose performance segment that Venice is targeting. AMD already holds a record 46% server CPU revenue share as of Q1 2026, according to Mercury Research, up from roughly 40% at the company's Financial Analyst Day in November last year. Venice will likely extend that momentum into a segment where Intel will be relying on its existing Granite Rapids Xeon 6 lineup for at least another year. AMD also confirmed Verano, another 6th Gen EPYC processor built on TSMC 2nm and optimized for performance-per-dollar-per-watt. AMD also says it plans to ramp Venice production at TSMC's Arizona facility. That's likely referring to Fab 21 Phase 3, which broke ground last April and is slated for N2 and A16 processes. Volume 2nm production isn't expected before 2028 at the earliest here, however. Follow Tom's Hardware on Google News, or add us as a preferred source, to get our latest news, analysis, & reviews in your feeds.

AMD EPYC Venice Enters Production on TSMC 2nm Process

AMD has announced that its next-generation EPYC processor, codenamed Venice, is ramping production in Taiwan on TSMC's advanced 2nm process technology. The company also plans to ramp production at TSMC's Arizona fabrication facility at a later stage, giving the platform a broader advanced manufacturing footprint. Venice is the next major step in AMD's data center CPU roadmap and is aimed at cloud, enterprise, HPC, and AI infrastructure. AMD states that the processor is the first high-performance computing product to enter production on TSMC's 2nm process. That makes the announcement notable not only from a product roadmap perspective, but also as an indicator of how quickly advanced nodes are moving into server-class silicon. The CPU remains a critical part of AI infrastructure. While accelerators handle much of the raw AI compute, the processor is still responsible for system orchestration, data movement, storage, networking, and security tasks. As AI workloads scale beyond training and inference into more complex agentic workloads, AMD is positioning Venice as a platform designed to support these broader infrastructure requirements. AMD also confirmed that its future EPYC processor Verano will use TSMC 2nm technology. Verano is described as a 6th Gen EPYC processor optimized for performance-per-dollar-per-watt. AMD also mentions advanced memory innovations, including LPDDR, which points toward a focus on bandwidth, efficiency, and power-constrained server environments. The announcement further underlines AMD's continued reliance on TSMC for both advanced process nodes and packaging technologies. AMD references TSMC SoIC-X and CoWoS-L as part of its broader AI and data center portfolio. These packaging technologies are increasingly important as modern compute platforms combine CPUs, accelerators, memory, and interconnects into more integrated designs. With Venice now ramping on 2nm, AMD is preparing its next EPYC generation for a data center market increasingly shaped by AI infrastructure, efficiency targets, and platform-level scaling. Source: AMD

AMD's EPYC Venice Becomes Industry's First 2nm HPC CPU To Achieve Volume Ramp As It Races Towards Agentic AI Leadership

AMD's EPYC Venice CPUs have entered volume production, making them the first HPC product to achieve the milestone on TSMC's 2nm process tech. The Agentic AI boom is driving the CPU market up, unlike anything that came before. High-Performance CPUs are seeing massive demands, and AMD, being a leader in HPC, has just achieved volume ramp of its next-generation EPYC Venice CPUs based on the Zen 6 core architecture. The volume ramp was achieved on TSMC's cutting-edge 2nm process technology. Looking ahead, AMD plans to achieve volume ramp for the same EPYC Venice CPUs at TSMC Arizona, further enhancing its manufacturing capacity to fulfill the demands of AI datacenters and Enterprises. AMD will also extend TSMC's 2nm process technology to its next-generation "AI-Focused" CPU called Verano, which is a version of Venice designed specifically for Agentic AI workflows and features the latest memory standards, such as LPDDR, providing the performance, bandwidth, and efficiency advantage for AI. AMD and TSMC's partnership spans the technologies needed to scale modern data center computing, from TSMC 2nm process technology for next-generation CPUs to advanced packaging technologies, including TSMC's SoIC-X and CoWoS-L, used across AMD's broader AI and data center portfolio. With "Venice" ramping on TSMC 2nm, AMD is advancing the CPU foundation for AI infrastructure while continuing to leverage TSMC's process and packaging leadership to deliver increasingly integrated compute platforms at scale. AMD The 6th Gen AMD EPYC family will be codenamed Venice, and will feature the Zen 6 core architecture. AMD's EPYC Venice CPUs will offer over 70% improvement in performance and efficiency. This is quite massive and shows us what Zen 6 is capable of, even if this lineup only represents the server segment. In addition to the performance and efficiency improvement, AMD's EPYC Venice CPUs will also offer over 30% improvement in thread density. These CPUs will come in two options: classic 96-core and denser 256-core variant. The 256-core and 512-thread processors mark a 33.3% improvement versus the existing Turin lineup, which maxes out at 192 cores and 384 threads. We should now roll back to the >70% performance and efficiency improvement. These numbers are solid since a 33.3% increase just from the core count increase is represented, but the rest should come from IPC, clock rate, and other architectural improvements. The TSMC 2nm process technology transitions from FinFET to Nanosheet transistors (GAA), and offers 10-15% higher performance at the same power, 25-30% lower power consumption at the same performance, and up to 15% higher transistor density. AMD is set to have a heated battle later this year as other firms also gear up to release their own CPUs to address the growing Agentic AI demands. We have seen NVIDIA claiming to become the leading CPU supplier in 2026 with its Vera CPU, racking in an estimated $20 billion in revenue, the Arm AGI CPU, and Intel doubling down on its own CPU efforts. Given AMD's close relations with TSMC, and since Lisa Su herself made a surprise visit to Taiwan, ahead of Computex 2026, reported to secure 2nm capacity for its EPYC Venice CPU, followed by the multi-billion dollar investment across various Taiwanese firms, and then the announcement by TSMC itself, AMD is looking very strong as it enters a contested CPU space. But in all of this, volume and supply matter, and regardless of the chip, whoever provides the most volume is going to be the winner in the Agentic AI race.