DeepSeek to train V5 AI model on 160,000 Huawei Ascend 950DT chips in full domestic stack shift

DeepSeek Pivots to Domestic Hardware for V5 Training

The Chinese AI company DeepSeek is preparing to train its V5 AI model using 160,000 Huawei Ascend 950DT chips at a new facility in Ulanqab, Inner Mongolia, with operations scheduled to begin in late 20261

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. This represents a strategic shift toward domestic full-stack AI infrastructure, moving away from the company's previous reliance on Nvidia hardware for high-performance workloads2

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. DeepSeek has placed orders worth approximately $2.56 billion for Huawei chips, with each Ascend 950DT chip priced at around 111,000 Yuan or roughly $16,0002

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. Deliveries are expected to ramp up in Q4 2026 to populate the company's 1GW data center2

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Testing Huawei's AI Model Training Capabilities

DeepSeek initially plans to assess the Huawei chips for inference, the process through which AI models generate responses to user requests, before using them for pre-training, which requires models to process large volumes of data1

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. The upcoming V5 model is expected to feature approximately 8-trillion-parameters, making it one of the most ambitious AI model training projects on domestic Chinese hardware2

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. This move comes after DeepSeek experienced stability and performance problems while training models on earlier generations of Huawei Ascend chips1

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. If successful, this would mark China's first AI training run completed on a wholly domestic hardware stack, complemented by the CUDA-like TileLang compiler2

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Advanced Specifications of Ascend 950DT Architecture

Huawei designed the Ascend 950DT for both AI model training and inference workloads. Each chip features 144 GB of high-bandwidth memory and approximately 4 TB/s of memory bandwidth1

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. Built on Huawei's self-developed third-generation DaVinci v3 architecture, the chip leverages SMIC's N+3 process technology, an advanced 7-nanometer class process2

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. The chip comes equipped with specialized High Bandwidth Memory (HiZQ 2.0 HBM), achieving a 2.0 TB/s GPU-to-GPU interconnect speed, and natively supports low-precision formats such as FP8, FP4, and Huawei's proprietary HiF82

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Atlas SuperPoDs Deliver Massive AI Compute Power

Huawei features the Ascend 950DT within its Atlas 950 SuperPoD infrastructure, which links up to 8,192 chips to deliver 8 EFLOPS of peak AI compute power2

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. These Atlas SuperPoDs feature 2 TB/s card-to-card interconnects and offer raw compute power of 8 EFLOPS on FP82

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. DeepSeek and Huawei recently optimized the 128-card version of the Ascend 950 Atlas SuperPoD, where the sparse attention operator achieved 410 TFLOPS in the read phase, allowing workloads to approach 95 percent of the chips' theoretical FP8 mathematical peak on isolated, compute-bound tasks2

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DeepSeek's Optimized AI Infrastructure Stack

DeepSeek has brought its AI infrastructure stack to Huawei's Ascend GPUs, featuring high-value components including DeepSelect for high-performance TopK kernels, TileLang for optimizing AI kernels, DeepGEMM-Ascend for optimizing GEMM kernels, DeepEP-Ascend for expert-parallel communication, TileKernels for vector compute and memory-access kernels, and FlashMLA for optimizing MLA attention kernels2

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. The TileLang compiler stands out as the most significant addition, allowing enterprises to write code in TileLang from the start, where chip vendors need only perform a single backend adaptation, with programs auto-selecting the underlying implementations at runtime2

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. This optimization has increased each chip's Model FLOPS Utilization to 45 percent, a significant improvement relative to the MFU of around 30 percent previously reported for Huawei's 910C chips2

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Implications for China's AI Hardware Landscape

The V5 training run will validate whether the TileLang hardware-agnostic intermediate layer route can support a full pre-training lifecycle for a frontier model, according to Chinese business experts2

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. If successful, the narrative of domestic compute competition shifts from comparing TFLOPS to H100 toward evaluating which chip has deeper backend adaptation to TileLang and whose supernode offers more reliable long stable training2

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. Nvidia's share in China's AI chip market has already dropped from 95% to 8%, with Ascend reaching 50%2

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. If the V5 model succeeds, CUDA's status as the default option could face its first structural fissure on China's AI training side, fundamentally altering how next-generation model training code is developed2

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