IBM unveils sub-nanometer chip with 100 billion transistors to power next-gen AI computing

IBM claims world's first sub-1 nanometer chip technology

A new chip architecture from IBM can integrate nearly 100 billion transistors on a chip the size of a human fingernail -- nearly twice the transistor density of the company's previous generation of chip technology. The resulting improvement in chip compute performance and energy efficiency comes from what IBM describes as the "world's first sub-1 nanometer chip technology" for AI data centers. "It's not just an incremental step, it's a meaningful leap forward," said Jay Gambetta, director of IBM Research and IBM Fellow, in an advance media briefing. He described the new chip technology as "pointing to a future where computing becomes significantly more powerful without a corresponding increase in energy." It's worth unpacking what the "world's first sub-1 nanometer chip technology" means, because it is impractical to build reliably functional chips with transistors and other features smaller than 1 nanometer due to various physical limitations. Instead, IBM is basically claiming that its new "nanostack" architecture can deliver the computing performance improvements that would be expected if a theoretical chip could be built with physical features smaller than 1 nanometer. Specifically, IBM describes its new chip technology as being built at the 0.7-nanometer node, which it has named the 7 angstrom node because one nanometer consists of 10 angstroms. But keep in mind that such node numbers have nothing to do with the actual physical dimensions of IBM's chip features. Older generations of chips developed in the 1970s and 1980s had physical features with dimensions matching the number in the name of their chip technology's node or process -- such as chips made at the 180-nanometer node -- but that has not been the case for decades and certainly not for the latest chip generations made with a 3-nanometer or 2-nanometer process. To overcome the physical scaling limits facing modern chip designers, IBM's new nanostack architecture vertically stacks transistors in a staggered layout to pack more transistors into the same chip space. The nanostack architecture builds on the company's prior development of nanosheet transistors that paved the way for its 2-nanometer chip node introduced in 2021. The basic unit of IBM's nanostack architecture consists of two transistors stacked and bonded together. Each transistor consists of three nanosheets that are individually 5 nanometers thick, equivalent to about 15 rows of silicon atoms. There is also a distance of about 9 nanometers separating each nanosheet. Performance gains for the AI era The nanostack architecture could pave the way for 50 percent higher computing performance or 70 percent greater energy efficiency than IBM's previous generation of 2-nanometer node chips, according to projections from the company's published technical reports. The company introduced its nanostack transistor architecture at the 2025 IEEE Symposium on VLSI Technology and Circuits held in Kyoto, Japan. IBM researchers also showed how the nanostack architecture can provide 40 percent improvement in scaling for static random-access memory (SRAM) during the VLSI 2026 symposium. SRAM allows for fast but energy-intensive read and write operations that are crucial in many AI applications. The memory improvement is made possible through a staggered-channel design for the chip's SRAM bit cells -- memory storage units consisting of six transistors -- that reduces overall cell height by 40 percent and enables more SRAM to be squeezed into the same chip space. That will probably be welcome news for chip designers looking to support AI workloads, given how SRAM scaling has fallen off drastically in recent generations of chip technologies. For example, SRAM scaling improved just a few percent between the 3-nanometer chip generation and the 2-nanometer chip generation, Gambetta explained. "This achievement of 40 percent will eventually industrialize itself in AI workflows, which require higher bandwidth and high efficiency," Gambetta said. The roadmap for sub-1 nanometer nodes As a company that performs chip technology research, IBM does not manufacture commercial chips that could end up in AI data centers or consumer devices. Instead, IBM has partnered with semiconductor companies such as Rapidus in Japan to mass manufacture its previous generation of 2-nanometer node chips based on the nanosheet architecture, or to commercialize related technology in another partnership with Samsung in South Korea. Other companies have followed up on IBM's pioneering work without any direct collaboration. For example, Taiwan's TSMC independently developed nanosheet transistors for its own proprietary 2-nanometer node technology. "Nanosheet has become the foundation of the next generation of transistor scaling," said Huiming Bu, vice president of IBM Semiconductors Global R&D and IBM Research, during the media briefing. "Today, nanosheet is adopted by all leading foundries for most of the 3-nanometer chips and all of the 2-nanometer chips." IBM declined to name specific companies that it may partner with to commercialize the newest sub-1-nanometer node technology. But Bu expects that commercial chips made at the sub-1-nanometer node and incorporating the newest nanostack architecture could begin production as early as in the next five years and most likely within a decade. "It will replace nanosheet as today's mainstream in leading foundries, whether it's CPUs or GPUs," Bu said. "Within a decade, this will become another mainstream that we have invented and helped industry to transform."

IBM says it can fit nearly 100 billion transistors on a chip - why the milestone matters

Follow ZDNET: Add us as a preferred source on Google. ZDNET's key takeaways * IBM's sub-1-nanometer NanoStack architecture holds almost 100 billion transistors on a chip. * These chips are cheaper to run and more powerful than previous generations. * NanoStack technology will be great for deploying AI workloads. TSMC, Intel, and Samsung have all been pushing to produce low‑single‑nanometer chips in the next two years, while planning to produce sub-nanometer chips sometime by decade's end. That race may be over, however, even before it began. IBM unveiled what it says is the world's first sub-1-nanometer chip technology based on a new 3D NanoStack transistor architecture at the 0.7 nm -- or 7 angstrom -- node. The research device, introduced ahead of VLSI 2026, is designed to pack nearly 100 billion transistors on a fingernail‑size die, roughly doubling the density of IBM's earlier 2-nm test chip, first shown in 2021. Today, the smallest, most powerful chips top out at about 80 billion transistors. Also: Why your RAM options cost 4X more now than last year - even legacy tech prices aren't immune What's so important about teeny-tiny chips? They're valuable because they let you pack more transistors into a given area while using less power, which translates into higher performance, lower energy use, and lower cost per unit of compute. In case you've been living under a rock, AI demands low-power, cheap chips. There's a huge market for these chips. From nanosheet to 'nanostack' At the heart of the announcement is NanoStack. This is a three‑dimensional, nanosheet‑based transistor design that scales vertically, or along the z‑axis, by stacking and staggering CMOS devices. Unlike today's nanosheet architectures, which IBM also pioneered and which are being adopted by leading foundries at 3 nm and 2 nm, NanoStack bonds two nanosheet transistors into a single vertical structure, with each tier optimized independently and contacted from opposite sides. Each transistor in the demonstrated structure uses three sub-5 nm‑thick nanosheets, about "15 silicon atoms" across, separated by roughly 9 nm spacers. Two such devices are then bonded vertically using an ultra‑thin dielectric process IBM describes as a key innovation. Because the top and bottom devices can use different channel materials, dielectrics, and metals, IBM argues NanoStack is less a single trick and more a transistor platform that can be extended through multiple generations: 7 angstrom (Å), 5 Å, 3 Å, and potentially down to 1 Å in its internal roadmap. Also: How much RAM does your PC need in 2026? My advice after using Windows and Mac for years An angstrom, by the by, is one ten-billionth of a meter. In terms of chips, an angstrom is a tenth of a nanometer. "This is the world's first sub‑1 nanometer chip technology with a new transistor architecture," said Jay Gambetta, Director of IBM Research and IBM Fellow, during a press briefing. "We're not just making smaller transistors, we're reinventing how chips are built to deliver dramatically more power and energy efficiency." Projected gains: performance, efficiency, and SRAM density IBM is positioning the 0.7 nm technology as a meaningful step beyond today's nanosheet nodes rather than just another incremental shrink. Based on internal benchmarking against its 2 nm node, the company said its new chips will deliver up to 50% higher performance at the same power, or up to 70% lower power for the same performance. Big Blue also highlighted a 40% improvement in the scaling of static random-access memory (SRAM) cell area relative to its 2 nm technology. This is a change IBM described as a "step the industry hasn't seen in over a decade" and one that could be particularly important for AI accelerators that live or die on on‑chip memory bandwidth. In the lab, IBM said it has experimentally validated the architecture with ultra‑thin dielectric bonding in a CMOS process, demonstrated dual‑channel engineering across the stacked devices, and shown functional CMOS inverters with expected switching behavior. "Together, these results confirm the nanostack technology can be physically built and supports real computation," the company said in its press materials. Angstrom‑class scaling, High‑NA EUV, and materials IBM is explicit that "0.7 nm" and "7 angstrom" should be read as generational node names, not literal gate lengths or pitches, in line with the broader industry trend of decoupling node labels from specific physical dimensions. Internally, the company said it benchmarked NanoStack's critical dimensions -- such as gate pitches and contacted gate pitch -- against a projected 1 nm‑class node, then pushed scaling by going vertical. To get there, the Albany research line leans heavily on advanced lithography and materials work. IBM and partners in New York, including ASML, Lam Research, Tokyo Electron, and SCREEN, are already installing a High Numerical Aperture EUV (High‑NA EUV) tool, the company calls "essential for the future of logic scaling," and are evaluating new metal‑oxide resists for patterning at angstrom‑class nodes. On the device side, NanoStack's separation of top and bottom transistors opens the door to introducing new channel materials and dielectrics on a per‑tier basis without having to qualify them across an entire planar CMOS stack. Also: I compared virtual RAM with real RAM on my Windows PC - here's what the numbers told me According to Huiming Bu, IBM's VP of silicon technology R&D, NanoStack is a new paradigm. It's moving chips to scaling fully into three dimensions and giving the industry at least "another decade" of logic advances as it crosses from nanometers into angstroms. Don't get too excited quite yet, though. Historically, introducing any genuinely new material into high‑volume CMOS has taken well over a decade. However, IBM argues NanoStack's partitioned architecture can reduce that friction. Still, university device researchers are already approaching IBM to explore new materials within the architecture. AI, data centers, and commercialization timeline Although the 0.7 nm chip demonstrated today is a research project, IBM is already tying the work directly to AI and cloud roadmaps. Gambetta and Bu both framed the performance‑per‑watt gains as crucial to accommodating runaway AI demand without equally runaway power bills, particularly in data centers where electricity and cooling are now defining constraints. "Everyone demands more performance, but no one wants to pay the bill for the power," Bu said. "This new innovation can improve performance by 50% compared to the best available chip today, and at the same time can reduce power by 70% if you choose to manage your power in that computing, which is a very critical component for AI." The 40% SRAM density bump could also help architects push caches and on‑die memory closer to compute units, cutting data movement overhead in training and inference workloads. IBM stressed that NanoStack is a generic logic technology. It's not a one-off or special‑purpose structure. IBM expects NanoStack to eventually underpin CPUs, GPUs, mobile SoCs, and SRAM arrays. While it is currently focused on bringing its nanosheet‑based 2 nm process into manufacturing with Japanese foundry partner Rapidus, IBM said NanoStack is intended to replace nanosheet as the mainstream leading‑edge architecture starting at the sub‑1 nm node. With that caveat, the company is still talking about selling its chips in the future. Drawing on its history of transferring nanosheet IP and other device innovations to commercial foundries, IBM said it sees a path to production use of NanoStack at a sub‑1 nm node "in as early as the next 5 years."

IBM stacks up a sub-nanometer chip future

Big Blue shows off process node it claims can scale down to 1 Angstrom IBM has developed a sub-nanometer (nm) chip technology it says could be used to produce commercial chips within five years, and has mapped a path to 0.1 nm. Big Blue claims its new process node can cram nearly 100 billion transistors onto a silicon die the size of a fingernail, almost double the density of the 2 nm technology it unveiled back in 2021. The new process as disclosed is actually for 0.7 nm or 7 Angstroms (7A), compared with the cutting-edge manufacturing nodes now being prepared for production in 2028 by the likes of Intel and TSMC which are 1.4nm, or 14 Angstroms. Several structural and material innovations have gone into this latest manufacturing method, including a three-dimensional nanostack architecture that sees transistors stacked, with n-type and p-type field-effect transistors (FETs) arranged so that one is layered above the other. "We're announcing it's not just an incremental step, it's a meaningful leap forward, enabling up to 50 percent higher performance, or 70 percent greater efficiency [than 2nm], and pointing to a future where computing becomes significantly more powerful without a corresponding increase in energy," claimed director of IBM Research and IBM Fellow Jay Gambetta. And the firm sees a clear path to shrinking down to one-tenth of a nanometer over the next ten years, he added. "Nanostack is not one innovation. It is actually a device platform that can enable the future of scaling for another decade beyond nanosheet, as you can see from our technology roadmap all the way to 1 Angstrom." Although the firm touts nanostack as the industry's first three-dimensional, nanosheet-based design, Intel was talking about 3D stacking of transistors back in 2023 - though has not so far implemented it. Huawei has also come up with a similar concept in its LogicFolding architecture, using two separate wafers fused together. IBM's nanostack design also has a twist - the transistors in the upper layer are staggered, or offset, from those below. "Nanostack is nanosheet transistors stacking on top of each other. But it's not through a simple monolithic lithography and etch process," said Huiming Bu, VP of Silicon Technology Research & Development at IBM. "What happens here is we actually stack in vertical direction but also stagger, so the front side of each transistor and the backside of each transistor can be contacted independently for signal and power," he added. "Second, the stacking of this transistor is done by single dielectric bonding, which is a key innovation that we have developed. Through that technology, the channel materials, essentially the top FET and the bottom FET, can be optimized independently." IBM says the architecture could support multiple applications such as CPUs, GPUs, mobile chips and memory, such as SRAM. Gambetta hinted that the technology could be used in future AI accelerators. "This is why we were excited by the initial experiment that shows a 40 percent scaling in SRAM. There are many examples of AI chips that are using more SRAM to scale, but fundamentally, it comes down to: can we make transistors more efficient, less power, put more in there?" he said. But IBM no longer manufactures chips itself. When asked which foundry might adopt its sub-nanometer process, Huiming said the nanosheet architecture IBM invented is now used by all leading foundries at this point. "I'm not going to talk about a business model, but it's being adopted by all leading foundries. But today, we are focusing on helping Rapidus to be successful in bringing up 2 nm manufacturing capability in Japan," he stated. Rapidus is a government-backed semiconductor foundry set up to revitalize the nation's semiconductor industry. The nanostack transistor architecture is discussed in a paper, available for download from the IEEE. ®

IBM unveils tech for chip smaller than 1 nanometer in AI computing push

June 25 (Reuters) - IBM (IBM.N), opens new tab on Thursday unveiled what it said was the world's first technology capable of producing chips smaller than one nanometer, as tech companies race to build semiconductors that can handle increasingly demanding AI workloads. Shares of the Armonk, New York-based company rose over 6% in premarket trading. They have fallen about 11% so far this year. The announcement comes at a time when chipmakers are searching for ways to maintain the decades-long trend of cramming more computing ⁠power into smaller spaces, a phenomenon known as Moore's Law. The new chip technology, which bolsters IBM's position to compete with contract chipmakers TSMC (2330.TW), opens new tab and Intel (INTC.O), opens new tab, has a transistor architecture of 0.7 nanometers, or 7 angstroms. Last week, Intel said the new generation of its 18A manufacturing process, which makes 1.8 nanometer chips, moved into risk production, the testing phase before commercial manufacturing. IBM said the 0.7-nanometer chip packs nearly 100 billion transistors onto a fingernail-sized surface, about twice the density ⁠of its 2-nanometer chip unveiled in 2021, delivering up to 50% higher performance or 70% greater energy efficiency. To get there, IBM developed a new transistor design called "nanostack". Instead of laying transistors flat, the design stacks them on top of each other in ⁠three dimensions, fitting more into the same volume of space. "With our new nanostack architecture, we're not just making smaller transistors, we're reinventing how chips are built to deliver dramatically ⁠more power and energy efficiency," director of IBM Research Jay Gambetta said. IBM says production could begin within five years. The company has previously licensed ⁠chip technologies to Samsung (005930.KS), opens new tab and Japan's Rapidus. It has not announced a manufacturing partner for this technology. Reporting by Anhata Rooprai in Bengaluru and Stephen Nellis in San Francisco; Editing by Varun H K and Devika Syamnath Our Standards: The Thomson Reuters Trust Principles., opens new tab

IBM says new sub-nanometer architecture paves the way for the next decade of chip design

IBM says new sub-nanometer architecture paves the way for the next decade of chip design IBM Corp. today unveiled what it says is the world's first sub-one-nanometer chip technology, a research breakthrough that it said will fuel the next 10 years of semiconductor development and pave the way to atomic-level chip design. The new technology is based on a transistor architecture IBM calls nanostack, designed for the 0.7-nanometer, or seven-angstrom, node. IBM said the architecture can pack nearly 100 billion transistors onto a chip about the size of a fingernail (pictured), or nearly twice the density of the two-nanometer chip technology the company introduced in 2021. IBM said the technology is projected to deliver up to 50% better performance and 70% greater energy efficiency compared with its two-nanometer node chips. The company also cited a 40% improvement in static random-access memory scaling, a development it said could be significant for artificial intelligence systems that need high-bandwidth, high-efficiency memory close to compute resources. "It's not just an incremental step, it's a meaningful leap forward... pointing to a future where computing becomes significantly more powerful without a corresponding increase in energy," said Jay Gambetta, director of IBM Research and an IBM Fellow. Nanostack builds on nanosheet technology, a transistor architecture IBM helped pioneer that has become the basis for leading-edge chips. Nanosheet was the industry's answer to the limits of fin field-effect transistors, the 3D transistor architecture used in modern microchips, so named for its raised, fin-like structure. Nanosheet improved transistor channel control, reduced power leakage and enabled scaling into the three- and two-nanometer generations. Nanostack is IBM's proposed next step beyond nanosheet, using vertical stacking to keep scaling going below 1nm. It adds a third dimension to chip scaling rather than relying solely on shrinking features across the wafer surface. Such innovations have kept semiconductor technology moving beyond physical limits of miniaturization, said Huiming Bu, vice president of silicon technology research and development at IBM. "When something is coming to an end, it doesn't mean the progress stops," he said. "What it means is that we need a new paradigm." He said the semiconductor industry has largely scaled metal-oxide-semiconductor field-effect transistors in two dimensions since the transistor was invented in 1959. Nanostack's vertical-stacking architecture allows designers to leverage the third dimension to increase density. "This will be for the first time in our industry that we are able to stack and stagger transistors in a vertical direction," Bu said. An IBM research paper published last year describes nanostack as a sequentially stacked complementary metal-oxide-semiconductor architecture with flexible placement of top and bottom nanosheet channels, ultra-thin dielectric bonding and a thermally stable bottom transistor gate stack. IBM said it has demonstrated the ability to manufacture nanosheet-on-nanosheet CMOS transistors, including functional CMOS inverters and electrical characteristics comparable to or better than non-stacked nanosheet baselines. The design allows the top and bottom transistors to be engineered separately and to use different materials for each layer. IBM said that flexibility could enable performance and power optimizations that are difficult in conventional transistor structures, where multiple components must be integrated on the same plane. The architecture could apply across multiple chip categories, including CPUs. graphics processing units and mobile processors. "This is a generic technology," Bu said. "We expect this architecture to be used for multiple applications." AI applications The potential uses in artificial intelligence are likely to draw particular attention because power consumption has become a constraint on data center expansion. As AI models grow and inference demand increases, chipmakers are under pressure to improve performance without forcing proportional increases in power, cooling and infrastructure costs. "Everyone demands more performance, but no one wants to pay for the bill for the power," Bu said. Gambetta said the SRAM scaling benefits are especially relevant because many AI chips rely heavily on on-chip memory to reduce data movement, which is one of the largest sources of energy consumption. More efficient SRAM designs could help increase cache capacity and reduce the need to move data between processors and external memory. IBM cautioned that the technology is on a research-to-manufacturing path rather than a commercial product. The company said it expects the earliest adoption of nanostack at the sub-nanometer node to come within the next five years. The work is being conducted at IBM's semiconductor research facility in Albany, New York, where the company and its partners are also preparing to use High Numerical Aperture Extreme Ultraviolet Lithography, a next-generation chipmaking tool developed by ASML Holding N.V. IBM said High NA EUV will be important for future logic scaling and could also improve nanosheet technology before nanostack reaches production. IBM said it's currently working with partners including Japan's Rapidus Corp. on two-nanometer manufacturing. Gambetta said IBM isn't yet disclosing how it will commercialize nanostack, saying the company's near-term focus remains helping partners scale nanosheet technology.

IBM unveils tech for chip smaller than 1 nanometer in AI computing push

IBM has unveiled groundbreaking chip technology capable of producing transistors at 0.7 nanometers, a significant leap towards smaller and more powerful semiconductors. This innovation, featuring a novel 'nanostack' architecture, promises nearly double the density of previous designs and could revolutionize AI capabilities. While commercial production is estimated to be five years away, this development intensifies the race among tech giants to meet the growing demand for advanced computing power. IBM on Thursday unveiled what it said was the world's first technology capable of producing chips smaller than one nanometer, as tech companies race to build semiconductors that can handle increasingly demanding AI workloads. Shares of the Armonk, New York-based company rose over 6% in premarket trading. They have fallen about ⁠11% so ⁠far this year. The announcement comes at a time when chipmakers are searching for ways to maintain the decades-long trend of cramming more computing power into smaller spaces, a phenomenon known as Moore's Law. The new chip technology, which bolsters IBM's position to compete with contract chipmakers TSMC and Intel, has a transistor architecture of 0.7 nanometers, ⁠or 7 angstroms. Last week, Intel said the new generation of its 18A manufacturing process, which makes 1.8 nanometer chips, moved ⁠into risk production, the testing phase before commercial manufacturing. IBM said the 0.7-nanometer chip packs nearly 100 billion transistors onto a fingernail-sized surface, about twice the density of its 2-nanometer chip unveiled in 2021, delivering up to 50% higher performance or 70% greater energy efficiency. To get there, IBM developed a new transistor design called "nanostack". Instead of laying transistors flat, the design stacks them on top of each other in three dimensions, fitting more into the same volume of space. "With our new nanostack architecture, we're ⁠not just making smaller transistors, we're reinventing how chips are built to deliver dramatically more power and energy efficiency," director of IBM Research Jay Gambetta said. IBM says production could begin within five years. The company has previously licensed chip technologies to Samsung and Japan's Rapidus. It has not announced a manufacturing partner for this technology.