IBM unveils sub-1 nanometer chip technology with 100 billion transistors for AI data centers
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IBM claims world's first sub-1 nanometer chip technology
A new chip architecture from IBM can integrate nearly 100 billion transistors on a chip the size of a human fingernail -- nearly twice the transistor density of the company's previous generation of chip technology. The resulting improvement in chip compute performance and energy efficiency comes
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IBM's New Chip Fits Nearly 100 Billion Transistors in the Size of a Fingernail
IBM on Thursday unveiled the first chip created using its latest semiconductor technologies, one that holds nearly 100 billion transistors in a fleck of hardware no bigger than your fingernail. Packing more transistors into a die the same size or smaller than previous generations is an essential
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IBM says it can fit nearly 100 billion transistors on a chip - why the milestone matters
Follow ZDNET: Add us as a preferred source on Google. ZDNET's key takeaways * IBM's sub-1-nanometer NanoStack architecture holds almost 100 billion transistors on a chip. * These chips are cheaper to run and more powerful than previous generations. * NanoStack technology will be great for
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IBM stacks up a sub-nanometer chip future
Big Blue shows off process node it claims can scale down to 1 Angstrom IBM has developed a sub-nanometer (nm) chip technology it says could be used to produce commercial chips within five years, and has mapped a path to 0.1 nm. Big Blue claims its new process node can cram nearly 100 billion
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IBM unveils tech for chip smaller than 1 nanometer in AI computing push
June 25 (Reuters) - IBM (IBM.N), opens new tab on Thursday unveiled what it said was the world's first technology capable of producing chips smaller than one nanometer, as tech companies race to build semiconductors that can handle increasingly demanding AI workloads. Shares of the Armonk, New
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IBM creates world's first sub-1nm computer chip -- cramming 100 billion transistors into a tiny fingernail-sized space
IBM's NanoStack architecture has helped scientists cram 100 billion transistors onto a computer chip, delivering 50% better performance and consuming 70% less energy than the current generation. For the first time, scientists can develop computer chips with transistors smaller than 1 nanometer.
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IBM unveils sub-1-nanometer chip architecture that stacks 100 billion transistors onto a fingernail-sized processor
Serving tech enthusiasts for over 25 years. TechSpot means tech analysis and advice you can trust. First look: IBM is once again testing the limits of chip design, this time with an architecture that moves beyond traditional scaling into a more three-dimensional layout aimed at AI workloads. The
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IBM says new sub-nanometer architecture paves the way for the next decade of chip design
IBM says new sub-nanometer architecture paves the way for the next decade of chip design IBM Corp. today unveiled what it says is the world's first sub-one-nanometer chip technology, a research breakthrough that it said will fuel the next 10 years of semiconductor development and pave the way to
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IBM announces world's first sub-1 nanometer chip with nanostack technology doubling transistor density
IBM has announced what it calls the world's first sub-1 nanometer chip technology, unveiling a new 0.7nm process built around an entirely new transistor architecture called nanostack. The result is a chip the size of a human fingernail that packs nearly 100 billion transistors, almost double the
[10]
IBM unveils tech for chip smaller than 1 nanometer in AI computing push
IBM has unveiled groundbreaking chip technology capable of producing transistors at 0.7 nanometers, a significant leap towards smaller and more powerful semiconductors. This innovation, featuring a novel 'nanostack' architecture, promises nearly double the density of previous designs and could
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IBM Unveils New Chip Technology That Breaks The 1 Nanometer Barrier
IBM's "nanostack" semiconductor architecture, which can pack nearly 1 billion transistors onto a single chip, offers performance and energy efficiency gains that could prove crucial as AI computing becomes increasingly widespread. VARs and system integrators could tap into the technology. IBM has
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IBM Unveils World's First Sub-1nm Chip Technology, New Era for AI Computing Begins
IBM has developed the world's first sub-1nm chip technology that could revolutionize semiconductor research. The advancement would not only make AI computations faster but would also help to develop advanced processor technology. The announcement comes as chipmakers look for new ways to sustain the
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IBM revealed the world's first sub-1 nanometer chip technology, packing nearly 100 billion transistors onto a fingernail-sized die using a new nanostack architecture. The breakthrough delivers up to 50% higher performance and 70% greater energy efficiency compared to IBM's 2-nanometer chips, with production expected within five years through partners like Rapidus.
IBM Introduces Breakthrough Nanostack Architecture for AI Computing
IBM has unveiled what it describes as the world's first sub-1 nanometer chip technology, a development that could reshape how the semiconductor industry approaches AI computing demands. The new chip technology integrates nearly 100 billion transistors on a chip the size of a human fingernail, achieving almost double the transistor density of IBM's previous 2-nanometer generation
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. Jay Gambetta, director of IBM Research and IBM Fellow, emphasized that this represents "not just an incremental step, it's a meaningful leap forward," pointing to a future where computing becomes significantly more powerful without a corresponding increase in energy1
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Source: Analytics Insight
The breakthrough centers on IBM's nanostack architecture, which vertically stacks transistors in a staggered layout to overcome physical scaling limits facing modern chip designers
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. Built at the 0.7-nanometer node—or 7 angstrom node, since one nanometer consists of 10 angstroms—this chip technology delivers projected performance gains of up to 50% higher computing performance or 70% greater energy efficiency compared to IBM's 2-nanometer node chips1
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.How Vertically Stacked Transistors Enable Semiconductor Innovation
The basic unit of IBM's nanostack architecture consists of two transistors stacked and bonded together through an ultra-thin dielectric process that IBM describes as a key innovation
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. Each transistor comprises three nanosheets that are individually 5 nanometers thick, equivalent to about 15 rows of silicon atoms, with a distance of approximately 9 nanometers separating each nanosheet1
. Unlike today's nanosheet architectures, which IBM also pioneered, the nanostack design bonds two nanosheet transistors into a single vertical structure, with each tier optimized independently and contacted from opposite sides3
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Source: CNET
Huiming Bu, vice president of IBM Semiconductors Global R&D and IBM Research, explained that the transistors in the upper layer are staggered or offset from those below, allowing the front side and backside of each transistor to be contacted independently for signal and power
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. Because the top and bottom devices can use different channel materials, dielectrics, and metals, IBM positions the nanostack architecture as a transistor platform that can be extended through multiple generations: 7 angstrom, 5 angstrom, 3 angstrom, and potentially down to 1 angstrom3
.SRAM Scaling Breakthrough Addresses AI Workloads Demands
IBM researchers demonstrated that the nanostack architecture provides a 40% improvement in SRAM scaling during the VLSI 2026 symposium, a development Gambetta described as "a step the industry hasn't seen in over a decade"
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. This memory improvement comes through a staggered-channel design for the chip's SRAM bit cells that reduces overall cell height by 40% and enables more SRAM to be squeezed into the same chip space1
. Static random-access memory allows for fast but energy-intensive read and write operations crucial in many AI applications2
.The timing matters because SRAM scaling has fallen off drastically in recent generations of chip technologies. For example, SRAM scaling improved just a few percent between the 3-nanometer chip generation and the 2-nanometer chip generation
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. "This achievement of 40 percent will eventually industrialize itself in AI workflows, which require higher bandwidth and high efficiency," Gambetta said1
. Bu emphasized that energy efficiency "is a very critical component for AI," noting that "everyone demands more performance, but no one wants to pay for the bill for the power"2
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Production Timeline and Manufacturing Partnerships
IBM says it "sees a path to production" within five years, though the company does not manufacture commercial chips itself
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. As a company that performs chip technology research, IBM has partnered with semiconductor companies such as Rapidus in Japan to mass manufacture its previous generation of 2-nanometer node chips based on the nanosheet architecture, and has collaborated with Samsung in South Korea to commercialize related technology1
. IBM has not yet announced a manufacturing partner for this sub-1 nanometer chip technology5
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Source: The Register
The announcement positions IBM to compete with contract chipmakers TSMC and Intel in the race to maintain Moore's Law—the decades-long trend of cramming more computing power into smaller spaces
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. Last week, Intel said the new generation of its 18A manufacturing process, which makes 1.8 nanometer chips, moved into risk production5
. TSMC and other leading foundries have independently developed nanosheet transistors for their own proprietary 2-nanometer node technology, following IBM's pioneering work1
.Implications for High-Performance Computing and AI Accelerators
The nanostack architecture could support multiple applications including CPUs, GPUs, mobile chips, and memory technologies
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. Gambetta hinted that the technology could be used in future AI accelerators, explaining that "there are many examples of AI chips that are using more SRAM to scale, but fundamentally, it comes down to: can we make transistors more efficient, less power, put more in there?"4
. IBM presented its nanostack transistor architecture at the 2025 IEEE Symposium on VLSI Technology and Circuits held in Kyoto, Japan1
.The development arrives as AI developers like OpenAI and Google race to build the most advanced models, requiring massive amounts of energy to train them, which can consume significant electricity, clean water, and land devoted to data centers
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. Creating more energy efficient chips represents a key piece of the AI-powered future that tech leaders envision, especially as current shortfalls in production capacity for memory, processors, and other components have created shortages in essential parts2
. IBM shares rose over 6% in premarket trading following the announcement5
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