Meta repurposes DDR4 memory in DDR5 servers with custom chip to cut AI infrastructure costs

Even Meta Is Using DDR4 to Get Around DDR5 Memory Shortages

The company reportedly uses a custom ASIC chip to ensure compatibility. Can we get that on some consumer boards, please? Meta is re-using its old DDR4 memory to fill gaps in its supply chain, and has a custom ASIC chip to make it work in DDR5-only systems, the company revealed at this week's International Symposium on Computer Architecture (ISCA). Even companies with near-unlimited budgets are struggling to get all the memory they need, and they're finding creative workarounds. TechSpot reports that Meta has been repurposing DDR4 memory from retiring servers in its new DDR5-only servers. With an AMD CPU and a terabyte of combined memory, each of the new "MemServer" designs pairs 768GB of DDR5 6400 with 256GB of DDR4 2400 memory. To connect these two memory types, Meta developed a Compute Express Link (CXL) 2.0 ASIC chip called Vistara, which enables "bridge DDR4 memory to host processors via a CXL 2.0/1.1-compliant PCIe Gen5 x16 interface." Each Vistara chip brings together two 72-bit DDR4 memory channels and can support up to 256GB per chip with up to 64GB per DIMM. However, in this example, Meta used 32GB DIMMS, "as this was the highest capacity available for reuse." This resulted in Meta using 128GB per chip, typically 4x32GB DIMMs, leaving room for expansion if it gains access to higher-capacity DIMMs. Meta's MemServer configuration details the broad performance difference between the two memory types. The 768GB of DDR5 delivers a local peak bandwidth of 614GB/s. In comparison, 256GB of DDR4 can deliver only a peak bandwidth of 76GB/s. Its idle latency is almost double that of the DDR5, too. This highlights how important DDR4 memory capacity is. With one-third the capacity, it can barely deliver 1/10 of the performance, but it does bring the server's combined memory to a terabyte. Meta explains that performance is less important with this configuration, noting that memory access patterns across its server workloads showed large portions of memory remaining idle for extended periods. "A small fraction of memory is accessed at any given moment, the rest is cold [...] Hence [using] a slower CXL-memory tier will minimally impact overall application performance. Since these pages are rarely accessed, the increased latency and reduced bandwidth of CXL memory are unlikely to become bottlenecks." This added capacity helps prevent servers from running out of memory, improves the retention rate of Meta hardware, reduces wear on SSDs and DDR5 memory, and lowers overall infrastructure costs. As Meta looks more to sell compute access to recoup some of its AI costs, selling the advantages of its server hardware designs may become key to its ongoing AI efforts.

Meta is using old DDR4 memory in DDR5-only AI servers to save on hardware costs

Serving tech enthusiasts for over 25 years. TechSpot means tech analysis and advice you can trust. Cutting corners: Faced with rising memory costs, Meta says it is reusing old DDR4 RAM in its servers rather than buying new hardware. The company revealed this week that it is repurposing DDR4 memory from decommissioned servers into its new DDR5-only machines, using a custom CXL ASIC that avoids the compatibility issues and major latency penalties that typically come with mixing memory generations. The design reportedly cuts AI inference server count by up to 25% and reduces job-restart and fragmentation overhead by 33%. Documents presented by Meta at ISCA 2026 this week reveal that its new "MemServers" are powered by AMD's Epyc Turin CPUs, featuring 158 cores and 316 threads. The Turin chips technically support only DDR5 RAM, but Meta got around that limitation with a custom CXL 2.0 ASIC called "Vistara," designed to let legacy DDR4 DIMMs work seamlessly alongside DDR5 platforms. Each MemServer packs 1 TB of combined memory, including 768 GB of DDR5-6400 local RAM and 256 GB of DDR4-2400 CXL-attached RAM connected via Vistara. Meta explained that Vistara's software stack treats the DDR4 memory as a "distinct, CPU-less NUMA node," separate from the local DDR5 DRAM nodes attached directly to the processor. Treating the two sets of DIMMs as separate nodes lets the system keep the most frequently accessed data in faster DDR5 memory while relegating cold pages to the slower DDR4 pool. The approach helps Meta optimize hardware resources and cut memory costs without meaningfully compromising performance. Meta's team also modified the Linux CXL driver to get the older DIMMs working on platforms that don't officially support them. The company noted that all Linux kernel CXL driver code used for Vistara is either already upstream or on track to be added to the codebase soon. Meta states that the Vistara ASIC was built to "bridge DDR4 memory to host processors via a CXL 2.0/1.1-compliant PCIe Gen5 x16 interface." Driven by custom RISC-V processors, each Vistara chip integrates two independent 72-bit DDR4 channels, supporting speeds up to 3,200 MT/s and capacities up to 256 GB per chip using 64 GB DIMMs. Meta is not the only company experimenting with combining DDR4 and DDR5 in the same system. South Korean fabless semiconductor firm Panmnesia says it has also developed a custom CXL controller and a CXL fabric switch with Port-Based Routing, giving hyperscalers another way to cut hardware spending. Like Meta, Panmnesia presented its CXL research at ISCA 2026 on June 29. The company said it plans to commercialize its new CXL products soon and is currently sampling its PCIe 6.4/CXL 3.2 Fusion Switch with select customers. Panmnesia is also developing a PCIe 7.0/CXL 4.0 Combo IP controller that adds support for the latest CXL 4.0 features.