Silicon Motion SM2524XT delivers 14 GB/s speeds to mainstream SSDs with AI optimization

New Silicon Motion SM2524XT chip brings 14 GB/s to mainstream SSDs -- 6nm DRAMless controller boasts heavy AI PC optimization and slashes KV cache latency

While high-end SSDs with eight-channel controllers approached peak read speeds of around 14 GB/s years ago, mainstream drives with quad-channel controllers often offer around 11 GB/s. However, with new types of 3D NAND that feature a higher-speed interface, it is possible to get to 14 GB/s with just four NAND channels. This is exactly what Silicon Motion's SM2524XT controller is designed to do: it has four NAND channels that support transfer rates of up to 4,800 MT/s and can offer up to 14 GB/s read speeds. Silicon Motion's SM2524XT controller is based on four (presumably Arm Cortex-R-series) cores, does not use DRAM, and complies with the NVM 2.0 specification. The unit has four NAND channels supporting data transfer rates of up to 4,800 MT/s as well as a PCIe 5.0 x4 host interface. The platform supports the latest types of 3D TLC and 3D QLC NAND and features SMI's NANDXtend LDPC ECC technology to cope with the inevitable read errors of the latest flash memory, though Silicon Motion hasn't disclosed the generation of the NAND or the codeword size. The company says the controller can deliver up to 2.5 million random IOPS alongside sequential read speeds reaching 14 GB/s, which is a very good result for mainstream solid-state drives. SMI uses TSMC's services to produce the controller using a 6nm-class process technology. Compared to its predecessor introduced about a year ago, the SM2524XT boosts random workload throughput by as much as 25%, reduces latency, and improves responsiveness during the fragmented read/write operations typical of KV cache and AI inference tasks. In fact, KV cache and enhanced AI inference performance are among the key advantages of the new SSD controller platform. "KV Cache has become a critical factor in AI inference performance, driving the need for sustained high random read/write throughput and low-latency data access," said Nelson Duann, Senior VP of Client & Automotive Storage Business at Silicon Motion. "As AI PCs evolve to support increasingly complex Local Agent and on-device LLM workloads, the SM2524XT is designed to deliver the random I/O performance, latency stability, and power efficiency required for next-generation AI storage architectures." KV cache is a storage area used by AI models to keep previously processed data so the model does not need to recalculate it for every new token. While this significantly reduces compute overhead, it also creates massive amounts of small, random, latency-sensitive memory and storage accesses. While this may not be a big problem in the data center environment, it may create performance bottlenecks when AI workloads run locally on a PC with a relatively limited DRAM capacity. As a result, latency and KV cache performance may limit the performance of long-context and multi-agent workloads. To address these performance penalties, the SM2524XT controller integrates several of Silicon Motion's technologies, including Separated Command Address (SCA) technology, which separates command and address traffic inside the NAND interface and enables the controller to process both simultaneously (rather than serially) to lower latency, increase effective bandwidth, and therefore maintain predictable performance. As an added bonus, these technologies make SM2524XT useful not only for PCs but also for edge AI devices. Silicon Motion will certainly demonstrate prototype drives based on its latest SM2524XT controller at the upcoming Computex trade show next week, which is when we learn when the company expects actual SSDs based on the chip to hit the market. Yet, it is safe to say that they are not going to arrive earlier than next year. Follow Tom's Hardware on Google News, or add us as a preferred source, to get our latest news, analysis, & reviews in your feeds.

Silicon Motion Unveils SM2524XT PCIe Gen5 DRAMless AI SSD Controller

Silicon Motion has announced the SM2524XT, a new PCIe Gen 5 DRAMless SSD controller developed for AI inference workloads and KV Cache-heavy storage operations. The controller targets next-generation AI PCs and local large language model deployments where sustained low-latency random performance is becoming increasingly important. The SM2524XT uses a new four-core processor architecture combined with PCIe Gen 5 x4 connectivity and NAND interface speeds reaching up to 4,800 MT/s. Silicon Motion rates the controller for sequential read throughput up to 14 GB/s and random performance up to 2.5 million IOPS. The company says the design is optimized not only for peak bandwidth, but also for maintaining stable random read and write performance during prolonged AI-driven workloads. Unlike conventional consumer desktop activity, AI inference and KV Cache operations generate highly fragmented and latency-sensitive access patterns. Those workloads can place sustained pressure on SSD controllers, particularly under thermal and power-constrained conditions. Silicon Motion positions the SM2524XT as a controller specifically engineered to maintain consistent response times and stable throughput under these conditions. The controller is manufactured on TSMC's 6 nm process node. According to Silicon Motion, the new design improves performance per watt by up to 25 percent compared to the previous generation controller while also increasing random workload performance by as much as 25 percent. Lower latency behavior is another major focus area, particularly for local AI workloads where storage responsiveness directly impacts inference speed and overall system behavior. Several proprietary technologies are integrated into the controller. Silicon Motion's Separated Command Address technology is designed to improve parallel NAND processing efficiency and reduce latency interruptions. The SM2524XT also integrates advanced FTL scheduling and NANDXtend LDPC ECC technologies to improve stability and maintain sustained performance consistency during extended workloads. The announcement reflects a broader transition occurring within the SSD market. Storage vendors are increasingly adapting products for AI-oriented client systems rather than focusing exclusively on gaming and traditional desktop usage. Local AI agents, on-device LLM execution, and edge inference workloads place different demands on storage hardware, particularly regarding random I/O throughput and latency consistency. The SM2524XT also highlights the growing importance of DRAMless controller designs in the PCIe Gen 5 segment. By balancing lower power consumption, reduced thermal density, and high sustained throughput, these designs are becoming increasingly relevant for compact AI systems and mobile workstation platforms.

Silicon Motion unveils PCIe Gen5 SSD controller for AI workloads By Investing.com

TAIPEI, Taiwan - Silicon Motion Technology Corporation (NASDAQ:SIMO) announced today the SM2524XT, a PCIe Gen5 DRAMless SSD controller designed for AI inference and KV Cache workloads. The company's shares have surged 366% over the past year, bringing its market capitalization to $9.7 billion. The SM2524XT features a four-processor-core architecture with PCIe Gen5 x4 interface and NAND interface speeds up to 4,800 MT/s. The controller achieves sequential read speeds up to 14 GB/s and random performance of up to 2.5 million IOPS, according to a press release statement. Built on TSMC's 6nm process technology, the SM2524XT delivers up to 25 percent higher performance per watt compared to the previous generation controller. The company states the new controller improves random performance by up to 25 percent versus its predecessor.Silicon Motion's strong product momentum has contributed to 36% revenue growth in the last twelve months. According to InvestingPro data, analysts anticipate continued sales growth this year, with five analysts revising earnings upward for the upcoming period. "KV Cache has become a critical factor in AI inference performance, driving the need for sustained high random read/write throughput and low-latency data access," said Nelson Duann, Senior VP of Client & Automotive Storage Business at Silicon Motion. The controller integrates Silicon Motion's Separated Command Address technology, advanced FTL scheduling, and NANDXtend LDPC ECC technologies. These features are designed to improve parallel data processing efficiency and reduce latency interruptions during sustained AI workloads. Silicon Motion supplies NAND flash controllers for solid-state storage devices and provides eMMC and UFS embedded storage controllers for smartphones, IoT products, and automotive applications.The stock currently trades near its 52-week high of $294, though InvestingPro analysis suggests it may be overvalued at current levels. Investors seeking deeper insights can access the comprehensive Pro Research Report, available for SIMO and 1,400+ other US equities. In other recent news, Silicon Motion Technology Corporation reported impressive financial results for the first quarter of 2026, surpassing market expectations. The company achieved an earnings per share of $1.58, exceeding the forecasted $1.28, which represents a 23.44% surprise. Revenue also outperformed predictions, reaching $342.1 million compared to the anticipated $299.61 million, marking a 14.18% increase. These financial achievements highlight the company's strong performance in the early part of the year. In addition to its financial success, Silicon Motion has received ISO 26262 functional safety process certification for automotive applications. This certification is an international standard for functional safety in road vehicles and covers various aspects of the company's automotive product development processes. The certification underscores Silicon Motion's commitment to meeting rigorous industry standards in its automotive segment. These developments reflect the company's ongoing efforts to enhance its market position and operational capabilities. This article was generated with the support of AI and reviewed by an editor. For more information see our T&C.