Sandisk and SK hynix Release First HBF Spec: 512GB Capacity, 3 TB/s Bandwidth for AI Inference

Sandisk and SK hynix unveil HBF spec -- up to 16-Hi NAND stacks, 3 TB/s bandwidth, UCIe

Sandisk and SK hynix on Tuesday formally introduced the High Bandwidth Flash (HBF) specification, their jointly developed storage technology that promises to bring together the non-volatility of 3D NAND and the performance of High Bandwidth Memory (HBM), which will be handy for AI inference systems. The specification was released through the Open Compute Project (OCP), so it will be an open standard rather than a proprietary interface. The initial specification defines HBF packages with capacities of up to 512GB using either 8-Hi or 16-Hi NAND die stacks, though these will not be standard 3D NAND stacks, but rather specialized devices with a fast interface. In fact, Sandisk once called them HBF core dies rather than 3D NAND die stacks. Performance of HBF is divided into three bandwidth grades ranging from approximately 0.4 TB/s to 3.0 TB/s (though we are not sure whether this figure describes the full HBF subsystem or per-package bandwidth). Such a huge performance range implies that Sandisk and SK hynix expect HBF to have a multi-year roadmap featuring multiple implementations and generations of HBF. It is noteworthy that the most capable implementation of HBF (3 TB/s) is set to beat the memory bandwidth of a single HBM4 memory stack (2 TB/s), though it will be unlikely to beat HBM4 when it comes to latency. Interestingly, SK hynix claims that HBF uses the Universal Chiplet Interconnect Express (UCIe) standard to simplify integration with heterogeneous computing platforms, whereas Sandisk claims that HBF is set to adopt the 'xPU-HBF' interface, which could be its definition of UCIe implemented by companies like Broadcom or Marvell. In addition to capacity and performance targets, the specification establishes electrical and interface characteristics, packaging and reliability guidelines for stacked HBF devices, as well as software I/O requirements. For now, these specifications are not officially published by the OCP. Extracting 400 GB/s of bandwidth from a single 512GB HBF package is not a trivial task. To enable such a package, Sandisk once planned to use 16 HBF core dies that feature many, many arrays that can be accessed concurrently using dedicated read/write paths. Meanwhile, it is possible to reach over 400 GB/s of bandwidth per package using a single UCIe interface that runs at up to 64 GT/s and features 64 lanes. Yet, this means that the HBF base die will be a fairly complex piece of silicon. Sandisk and SK hynix position HBF as a new memory tier for AI inference workloads by combining near-memory bandwidth with the higher capacity and non-volatility of NAND flash. The technology is aimed at workloads that require substantially larger memory pools close to compute than HBM alone can economically provide. For example, while the maximum capacity of an HBM4 stack is 64GB, an HBF stack can provide up to 512GB. Even at a lower bandwidth, such memory can be useful for inference workloads. Arguably the biggest question about HBF is who is going to adopt the technology? Since Sandisk and SK hynix announced plans to collaborate on defining the HBF specification in 2025, only Google and Tenstorrent have expressed interest in participating in the HBF consortium. Meanwhile, AMD, Broadcom, Intel, Nvidia, Marvell, Micron, Qualcomm, Samsung, and Western Digital have so far expressed no interest in HBF. Follow Tom's Hardware on Google News, or add us as a preferred source, to get our latest news, analysis, & reviews in your feeds.

High Bandwidth Flash gets first technical specification for AI data centers

Serving tech enthusiasts for over 25 years. TechSpot means tech analysis and advice you can trust. AI Gold Rush: Two of the world's "big three" memory manufacturers began collaborating on a new memory standard for accelerating AI workloads in 2025. Now, the first technical specification for High Bandwidth Flash memory is ready for major data center manufacturers to experiment with. A year ago, SanDisk and SK Hynix announced a collaboration to develop a common standard for the High Bandwidth Flash (HBF) project. The new type of memory is designed to improve performance and power efficiency in AI data centers and can now be implemented in new data center projects thanks to the newly announced HBF technical specification. The first HBF technical specification is part of the Open Compute Project, which means it should be freely available for adoption in custom data center projects or server designs. SanDisk and SK Hynix are the main contributors to the new specification, but other major AI industry players including Google and Tenstorrent have joined the standardization process with their own ideas and technology validation procedures. The HBF specification lays out the foundation for an HBF-ready rack or data center, defining the system interface, electrical requirements, and other technical guidelines needed to integrate HBF into a custom design. Furthermore, the specification includes "basic" performance expectations, the xPU-HBF host interface, and additional details on reliability and packaging for an HBF die stack. A software user guide covering read and write operations is also part of the specification. SanDisk developed HBF memory to combine the large storage capacity of NAND flash chips with the high-bandwidth data rates typically associated with High Bandwidth Memory products. The new HBF chips can vertically stack eight HBF layers, with a theoretical capacity of up to 4TB per chip. SanDisk CTO Alper Ilkbahar explained that HBF memory was conceived to meet the unprecedented memory demands of AI inference workloads and accelerators. Thanks to the new specification, system builders and data center operators now have a "practical path" to placing high-capacity memory and compute units or GPUs closer together. This significant milestone could also enable the creation of more flexible AI architectures. SanDisk and SK Hynix chose the OCP as a way to establish HBF as a de facto standard in the rapidly evolving AI memory market. The two companies expect the new technology to gain ground quickly among early adopters, which is an interesting proposition given the dire state of the semiconductor industry.

SK Hynix and SanDisk reveal first specs for High Bandwidth Flash -- but don't get too excited, you probably won't be able to buy it anytime soon

* The first HBF specification defines stacks of up to 512GB with three bandwidth grades from roughly 0.4TB/s to 3.0TB/s, connected to processors over UCIe and published openly through the Open Compute Project * Google and Tenstorrent have joined the consortium, but Nvidia is not among the named participants, which matters more to HBF's prospects as a de facto alternative to increasingly pricey HBM * Samples of the first AI inference devices built with HBF are expected to show up in early 2027 SK Hynix and SanDisk have published the first technical specification for High Bandwidth Flash. Released through the Open Compute Project to coincide with the opening of the Future of Memory and Storage conference, it makes for an impressively fast milestone, arriving six months after the HBF workstream was convened at SanDisk's Milpitas headquarters and a year after the two companies first agreed to standardize the technology. The solution, at least for now, exists only on paper, and has managed to draw two crucial partners to its consortium: Google and Tenstorrent. A promising standard, that focuses on capacity over raw speed High Bandwidth Flash's specification defines capacities up to 512GB across two stack configurations, 8-high and 16-high NAND dies, and sorts performance into three grades running from roughly 0.4TB/s to 3.0TB/s. HBF's pitch, unlike its competition, focuses on capacity rather than raw speed. A 512GB HBF stack sits against roughly 48GB to 64GB for an HBM4 stack, which is between eight and ten times the capacity, while the top HBF grade's 3.0TB/s lands inside the 2.0 to 3.3TB/s band typical of HBM4. It also adopts UCIe, the open chiplet interconnect standard, as the link between an HBF stack and a host processor, enabling the technology to be attached to GPUs and CPUs from different vendors. What could be challenging is delivering on its promise within a reasonable time; however, SanDisk has been working to a public roadmap since August 2025: first samples of the memory itself in the second half of 2026, and samples of the first AI inference devices built with HBF in early 2027. Neither company updated that schedule with this week's announcement. Industry expectations put actual commercialization somewhere between late 2027 and 2028, with the volume of data center demand that would justify the investment arriving closer to 2030, in a cycle that also involves partner testing followed by ramped-up production. This is despite SanDisk's Hsu telling SDxCentral in May 2026 that working through the Open Compute Project (OCP) let the effort move faster and that "you won't have to wait too long", which is a reasonable thing to say about a standard and a slightly generous thing to say about a product still eighteen months from sampling inside a device. SK Hynix is equally cagey when it comes to HBF's roadmap: the same document that announces HBF also unveils the company's tenth-generation 375-layer 4D NAND, claims a 2.5x improvement in performance per watt, and states plainly that mass production of enterprise SSDs built on it begins early next year; HBF gets no date mentioned at all. One interesting thing is that Nvidia is not among the named participants, even though it dominates the AI accelerator market. SK Hynix has, however, expanded a strategic partnership with Nvidia covering next-generation memory as recently as July 25, and that might be a sign that things could change, but there is no official confirmation from what is arguably the biggest AI player in the market just yet. Samsung, Micron and Kioxia are likewise absent, with Kioxia pursuing a different approach to the same problem. When HBF does eventually ship, it will probably not reach consumers in any shape or form until AI hyperscalers are sated and a viable interface for retail users is available to harness the tech. For now, HBF is unveiled but exists only on paper, allowing hyperscalers and accelerator designers to plan ahead for a technology that will become increasingly invaluable as the compute focus continues to shift from training to inference, with AI data centers coming online. Follow TechRadar on Google News and add us as a preferred source to get our expert news, reviews, and opinion in your feeds.

HBF Is For AI Model Weights, HBM Is For KV Cache

Buckle up as the ongoing memory- and HBM-related bottleneck is about to get materially decongested, thanks to SanDisk's initiative to develop High-Bandwidth Flash (HBF) in concert with SK hynix, which should eventually lead to a bifurcation in tasks that are currently performed solely by the HBM. HBF can offer read bandwidth that is orders of magnitude higher than what a JEDEC HBM4 offers, but suffers on write endurance Before discussing the HBF standard, let's first go over the memory wall issue that often comes up with HBM. HBM and the memory wall issue An AI model with 100 billion parameters and operating at fp16 compute level - so 2 bytes per parameter - requires 200GB (100x10⁹x2) of HBM just for storing model weights. For the benefit of those who might not be aware, weights tell a model how much importance it should accord to any given concept or a string of words. Basically, they are the sum total of a model's stored knowledge. As a general rule, the larger the model, the more weights it needs to store. But that's not all. Consider a scenario: you are writing a story, but hampered by terrible short-term memory. Whenever you write a new word, you are compelled to read whatever you've written so far just to remember what has already been inked. Obviously, as the text length increases, so does this laborious process. Key-Value or KV cache is similar to taking notes on a separate sheet so that you remain abreast of what has been written so far. This speeds up the entire process by orders of magnitude. Even so, as context increases so does KV cache, which is generally stored within the HBM given the speed and frequency with which a model needs to access it. Now comes the hard part. HBM4 stacks are soldered alongside the GPU and come equipped with limited memory bandwidth. For instance, a generic 12-Hi HBM4 stack holds 36GB of data, while its 16-Hi counterpart can push it to 48GB. So, HBM not only stores model weights but also KV cache. And, to increase HBM, you generally have to increase the GPU count, which can get very expensive very quickly. Now add HBF to this equation As we detailed earlier today, SanDisk is now developing an HBF standard with SK hynix, one that offers 512GB of storage along with a bandwidth of 0.4TB/s to 3TB/s. Basically, just as HBM stacks DRAM, HBF stacks NAND die on top of each other, with Through Silicon Vias (TSVs) connecting the dies together and a controller logic die bonded to this NAND array. The problem with using NAND cells, however, is their turtle-like speeds. An SRAM offers read speeds of just around a nanosecond vs. ~100 nanoseconds for DRAM and a whopping ~100 microseconds for NAND. This means that NAND offers 1,000x slower read speeds than a DRAM-based HBM. HBF, however, leverages the power of parallelism to increase bandwidth by orders of magnitude. Basically, the logic die schedules thousands of parallel reads of NAND cells simultaneously. So, while each individual read of a given NAND cell is around 1,000x slower, thousands of parallel reads can deliver a cumulative bandwidth of 0.3TB/s to 3TB/s vs. just around 6.4GB/s for a JEDEC-spec HBM4. Even so, an HBF can't counter NAND's atrocious write speeds and the attendant fragile write endurance. This means that KV cache will still need to be stored on the HBM as it requires frequent writes. Model weights, however, can shift to HBF. Now, as a final point, do note that HBF arrays are not expected to be SSD-level cheap, especially as they still require advanced packaging, which itself is a costly process. Even so, they can be quite a bit cheaper than HBM, which should unlock substantial economies of scale. Also, freeing up HBM for KV cache means model context can become longer without compromising on the underlying output accuracy, which adds another substantial benefit to this emerging paradigm. Follow Wccftech on Google to get more of our news coverage in your feeds.

Sandisk and SK hynix Unveil First Global High Bandwidth Flash Standard for AI

The specification provides companies and developers designing AI inference systems and accelerators with a common technical framework for incorporating HBF technology where larger, near-compute memory capacity and higher bandwidth are needed to improve power and performance metrics and help reduce total cost of ownership. Sandisk Corporation and SK hynix Inc. announced the release of the HBFTM (High Bandwidth Flash) technical specification through the Open Compute Project (OCP), advancing the workstream to drive HBF standardization for the AI inference era, just six months after the consortium began work in February. The specification was developed through the HBF technology workstream under OCP, with Sandisk and SK hynix serving as primary contributors. Notably, Google and Tenstorrent joined as consortium members during this standardization process, contributing significantly to technology validation and the establishment of the standard. The specification provides companies and developers designing AI inference systems and accelerators with a common technical framework for incorporating HBF technology where larger, near-compute memory capacity and higher bandwidth are needed to improve power and performance metrics and help reduce total cost of ownership. Modern AI inference systems need high-bandwidth memory positioned close to compute cores, while the demand for greater near-compute memory capacity continues to grow with the requirements of large language models and emerging AI workloads. HBF technology is designed to address this need by combining high bandwidth with high capacity, helping data center system designers improve interactivity and throughput during model serving. "AI inference is creating a new set of memory requirements, and HBF technology is designed to meet that moment," said Alper Ilkbahar, Chief Technology Officer, Sandisk. "This specification helps give system designers a practical path to bring high-capacity, high-bandwidth memory closer to compute, while enabling more flexible architectures. It is an important milestone for the HBF ecosystem and for the next generation of AI systems built to improve token economics at scale." The specification defines system interface, electrical and other technical guidelines for designing systems that interact with and use HBF technology, including basic performance expectations, the xPU-HBF host interface, reliability and packaging guidance for an HBF die stack, and a software user guide for read and write operations. As one of the first technical standards of its kind in the memory and storage industry, the specification helps give AI compute system designers added flexibility to build systems where HBF technology can coexist with High Bandwidth Memory, helping support ecosystem readiness. The specification was released within the Open Compute Project framework, meaning the information is openly available to the industry. Sandisk and SK hynix proactively published the specification to position HBF technology as the de facto standard in the rapidly evolving AI storage market. Their strategy involves fostering an early-stage ecosystem, increasing the visibility of HBF technology's adoption for customers, and accelerating market expansion and technological maturity through open collaboration and membership in the consortium.

SK hynix, In Collaboration With SanDisk, Unveils The New High Bandwidth Flash (HBF) Standard, Helping To Resolve AI Inference Bottlenecks, Targeting Up To 3TB/s Bandwidth

As AI accelerators face severe performance disparity between High Bandwidth Memory (HBM) and SSDs, SK hynix and SanDisk have collectively introduced a solution that aims to resolve the performance gap with a new standard called High Bandwidth Flash (HBF). Both memory manufacturers aim to create an ecosystem where various enterprises can develop compatible products. HBF specifications allow for up to 512GB in a single configuration that stacks NAND dies in eight or 16 layers In a nutshell, HBF possesses attributes that allow it to be positioned between HBM and enterprise SSDs. Similar to HBM, HBF relies on multiple memory dies that have been stacked together, but instead of DRAM, it utilizes NAND flash to increase storage capacity. Its primary role will be to complement capacity limits rather than outright replace HBM. LLMs can be processed through HBM, which is immediately required for computing, with HBF storing data in a larger capacity. SK hynix's and SanDisk's latest specifications allow for HBF to go as high as 512GB, with bandwidth ranging from 0.4TB/s to 3TB/s. To understand how the technology will benefit AI inference performance, assume that there's an AI model with 500 billion parameters, and if each gigabyte can house a billion parameters, that'll come to 500GB. Since it's not cost-effective to store the entire model in HBM, companies can leverage HBF to store these AI models. High Bandwidth Flash also supports the UCIe (Universal Chiplet Interconnect Express) specification, allowing HBF to connect to various CPUs and GPUs to introduce an entire flexibility layer. Kim Chun-sung, head of solution development at SK hynix, has said that the company "will expand the boundaries between memory and storage and contribute to building new architectures that enhance overall system efficiency." As SK hynix and SanDisk make efforts to popularize the HBF standard, Samsung is already establishing a healthy relationship with the likes of NVIDIA by developing and mass-producing CMX solutions. Through the manufacturing of its V10 and V11 NAND flash, which can reach up to 500 stacked layers, the Korean giant will target ultra-fast storage requirements for AI servers wanting to quickly access data to increase GPU offloading, leading to better AI inference. Which standard will pick up the pace? It looks like we'll find out in the coming months. News Source: SK hynix Follow Wccftech on Google to get more of our news coverage in your feeds.

Sandisk and SK hynix release standard specifications for High Bandwidth Flash (HBF) through OCP

At the Future of Memory and Storage (FMS) 2026 conference in Santa Clara, California, Sandisk Corporation and SK hynix Inc. announced the release of the first standard specifications for High Bandwidth Flash (HBF). Published through the Open Compute Project (OCP), the specification aims to establish HBF as an open standard to address memory bandwidth and capacity constraints in artificial intelligence (AI) inference workloads. The release comes six months after the formation of the HBF technology workstream under OCP in February 2026, following an initial standardization partnership between Sandisk and SK hynix in August 2025. During the standardization process, major industry entities -- including Google and Tenstorrent -- joined the consortium, participating in technology validation and standard formulation. Key Technical Specifications HBF technology introduces a memory layer positioned between High Bandwidth Memory (HBM) and Solid State Drives (SSDs). Designed to sit close to compute cores, it combines high-speed data transfer with high-density NAND capacity to reduce total cost of ownership (TCO) and support large language models (LLMs) and emerging AI workloads. * Capacity: Up to 512 GB, based on 8-high and 16-high NAND die stack configurations. * Bandwidth: Categorized into three grades (Grade 1 to Grade 3), providing scalable throughput ranging from 0.4 TB/s to 3.0 TB/s. * Host Interconnect: Adopts Universal Chiplet Interconnect Express (UCIe) to enable integration across various processor types, including GPUs, CPUs, and specialized xPUs. * Technical Guidelines: Defines connection interfaces, electrical characteristics, reliability and packaging standards for HBF die stacks, alongside software user guides for read/write I/O operations. By publishing the specifications openly through OCP, Sandisk and SK hynix aim to build an early-stage ecosystem, improve interoperability, and enable HBF to coexist alongside existing HBM architecture. FMS 2026 Presentations and Panel Sessions Both companies are highlighting HBF and tiered memory architectures through technical presentations and panels at FMS 2026: Keynote Sessions * SK hynix Keynote (August 4): Executive Vice President Kim Chun-sung and Vice President Kang Uk-song presented "Orchestrating Efficient AI Infrastructure through Tiered Memory in the Era of Agentic AI," focusing on multi-tier memory frameworks for scaling AI data demand. * Sandisk Keynote (August 5, 11:40 a.m. PT): Chief Revenue Officer Jim Elliott, Chief Product Officer Khurram Ismail, and Chief Technology Officer Alper Ilkbahar will present "NAND - The Versatile & Scalable Foundation of the AI Era," detailing system-level optimizations for AI inference. Joint Panel Discussion (August 6, 9:45 a.m. PT) A panel titled "Breaking the Memory Wall with High Bandwidth Flash" -- moderated by Thomas Coughlin (President, Coughlin Associates) -- will feature: * Rajeev Nagabhirava, Vice President, Sandisk * Lim Eui-cheol, Vice President, SK hynix * Xiaoyu Ma, Senior Staff Engineer, Google DeepMind The session will focus on architectural integration, performance economics, technical challenges, and standardization timelines for HBF. SK hynix Exhibits 375-Layer V10 4D NAND Alongside the HBF announcement, SK hynix revealed its tenth-generation (V10) 375-layer 4D NAND wafer and product prototypes for the first time. According to the company, the 375-layer 4D NAND achieves a 2.5x improvement in performance-per-watt compared to its previous generation, targeting power-sensitive data center environments. SK hynix plans to begin mass production of enterprise SSDs (eSSDs) based on the 375-layer process early next year, while displaying additional memory solutions across mobile, automotive, PC, and robotics applications at its exhibition booth.

SK hynix, Sandisk race to fix AI's next chip bottleneck

Anyone who bought a laptop or built a gaming PC this year already felt memory prices climb. DRAM and NAND flash have gotten steadily more expensive as AI data centers absorb nearly every chip factories can produce, according to a Bloomberg analysis. On August 3, SK hynix and Sandisk released the technical specification for a new memory category built to ease that exact scarcity, but the more interesting fight is over whose version of the fix becomes the industry standard. SK hynix, which also trades in the U.S. under the ticker SKHY, is the world's second-largest memory chipmaker and a dominant supplier of HBM for Nvidia's AI accelerators. Sandisk, trading as SNDK on the Nasdaq, spun off from Western Digital last year and specializes in NAND flash, competing directly with Samsung and Kioxia. Both stocks have surged over the past year as AI infrastructure spending has strained memory supply. The specification, called High Bandwidth Flash, defines a new memory tier positioned between HBM and solid-state drives, according to a joint statement from Sandisk and SK hynix. It supports capacity up to 512 gigabytes across stacks of eight or 16 NAND dies, with bandwidth split into three grades running from roughly 0.4 to 3.0 terabytes per second. No shipping product today combines flash-level capacity with anything close to HBM-level speed. HBM is fast because it stacks DRAM directly next to the processor, but DRAM is costly and limited in how much it can be packed. Solid state drives hold far more data for a fraction of the price, yet they are too slow for accelerators pulling live model data mid-inference. While AI training is building the model, inference is the process of running it live to generate responses for users. High Bandwidth Flash is designed to sit between the two, letting AI systems hold larger models closer to the chip without the delay of reaching for storage. Sandisk's own roadmap has targeted initial HBF samples for the second half of 2026, with AI inference products following in early 2027, according to the company's original announcement of the partnership. That puts real revenue at least a year away. Yuichiro Chino / Getty Images An open standard nobody has to license Google and Tenstorrent joined as consortium members during the standardization process, according to Sandisk's release. SK hynix and Sandisk published the specification through the Open Compute Project, an open industry framework, rather than keeping it proprietary, according to the Korea Herald. Letting any chipmaker build around a free specification is the fastest way to make it the default before a rival approach gains traction. Samsung and Kioxia are building rivals Samsung is expected to unveil its own next-generation architecture, called zHBM, at the same FMS 2026 conference this week, according to a BigGo Finance report. Unlike HBF, zHBM stacks memory directly on top of the GPU rather than beside it, and it sits outside the SK hynix and Sandisk consortium entirely. Samsung remains the world's largest NAND flash maker, giving it enough scale to push a competing approach regardless of which standard the rest of the industry adopts. Kioxia has taken a third path. The Japanese memory maker built a prototype High Bandwidth Flash module with 5 terabytes of capacity and 64 gigabytes per second of bandwidth over a PCIe interface, according to Kioxia's own announcement. That is a different connection standard than the UCIe interface SK hynix and Sandisk chose, so products built for one spec will not work with the other. For investors, that fragmentation is the risk sitting underneath an otherwise exciting technology story. Why the stock reaction undersells the news SK hynix (SKHY) and Sandisk (SNDK) shares gained roughly 3% in extended trading after the announcement. That reaction is hard to separate from timing. Sandisk reports fiscal fourth quarter earnings on August 5, just two days later, and the stock has swung between roughly $40 and $2,354 over the past year, a sign of how volatile memory names have become. SK hynix shares fell more than 9% in late July after a record quarter still missed revenue estimates, CNBC reported. Memory standards are becoming a competitive weapon The bigger story here is not a single spec sheet. Hyperscaler capital spending on AI infrastructure is on pace to exceed a trillion dollars this year, according to Deloitte, and memory makers are racing to make sure the architecture customers design around is theirs. That is what happened with HBM, where early movers locked in years of advantage before rivals caught up. High Bandwidth Flash is shaping up as the same fight one generation earlier, and this week's competing announcements out of Santa Clara suggest nobody has agreed yet on which version wins. For investors, the signal to watch is which GPU and hyperscaler partners standardize on which interface once products ship next year. The Arena Media Brands, LLC THESTREET is a registered trademark of TheStreet, Inc. This story was originally published August 4, 2026 at 12:13 PM.

Sandisk and SK hynix Advance Global Standardization of High Bandwidth Flash with Release of First OCP Technical Specification

Open Compute Project Specification provides foundation for High Bandwidth Flash adoption in AI inference systems Sandisk Corporation and SK hynix Inc. today announced the release of the HBFTM (High Bandwidth Flash) technical specification through the Open Compute Project (OCP), advancing the workstream to drive HBF standardization for the AI inference era, just six months after the consortium began work in February. The specification was developed through the HBF technology workstream under OCP, with Sandisk and SK hynix serving as primary contributors. Notably, Google and Tenstorrent joined as consortium members during this standardization process, contributing significantly to technology validation and the establishment of the standard. The specification provides companies and developers designing AI inference systems and accelerators with a common technical framework for incorporating HBF technology where larger, near-compute memory capacity and higher bandwidth are needed to improve power and performance metrics and help reduce total cost of ownership. Modern AI inference systems need high-bandwidth memory positioned close to compute cores, while the demand for greater near-compute memory capacity continues to grow with the requirements of large language models and emerging AI workloads. HBF technology is designed to address this need by combining high bandwidth with high capacity, helping data center system designers improve interactivity and throughput during model serving. "AI inference is creating a new set of memory requirements, and HBF technology is designed to meet that moment," said Alper Ilkbahar, Chief Technology Officer, Sandisk. "This specification helps give system designers a practical path to bring high-capacity, high-bandwidth memory closer to compute, while enabling more flexible architectures. It is an important milestone for the HBF ecosystem and for the next generation of AI systems built to improve token economics at scale." The specification defines system interface, electrical and other technical guidelines for designing systems that interact with and use HBF technology, including basic performance expectations, the xPU-HBF host interface, reliability and packaging guidance for an HBF die stack, and a software user guide for read and write operations. As one of the first technical standards of its kind in the memory and storage industry, the specification helps give AI compute system designers added flexibility to build systems where HBF technology can coexist with High Bandwidth Memory, helping support ecosystem readiness. The specification was released within the Open Compute Project framework, meaning the information is openly available to the industry. Sandisk and SK hynix proactively published the specification to position HBF technology as the de facto standard in the rapidly evolving AI storage market. Their strategy involves fostering an early-stage ecosystem, increasing the visibility of HBF technology's adoption for customers, and accelerating market expansion and technological maturity through open collaboration and membership in the consortium. Sandisk Keynote: NAND - The Versatile & Scalable Foundation of the AI Era On Wednesday, August 5, at 11:40 a.m. PT, Sandisk's keynote at The Future of Memory and Storage Conference (FMS) at the Santa Clara Convention Center, will explore the importance of system-level optimization and NAND in enabling AI inference at scale. The keynote will feature Sandisk's Jim Elliott, chief revenue officer; Khurram Ismail, chief product officer; and Alper Ilkbahar, chief technology officer. FMS Panel Discussion: Breaking the Memory Wall with High Bandwidth Flash On Thursday, August 6 at 9:45 a.m. PT, Sandisk, SK hynix, and Google will present a panel discussion hosted by Thomas Coughlin, President of Coughlin Associates, at The Future of Memory and Storage Conference (FMS) at the Santa Clara Convention Center, Conference Room D. The session will discuss how HBF technology aims to redefine the memory hierarchy by providing near-memory speeds with the density and persistence of high bandwidth flash. The panel will bring together experts from HBF solution providers as well as a Hyperscale-AI Infrastructure provider, to dissect the HBF technology usage and development needed for success, including Architectural Integration, Technical Challenges, Standardization timelines, performance and economics.

SK hynix, Sandisk unveil standards for high-bandwidth flash memory - The Korea Times

A concept image of high-bandwidth flash, the technology standards of which SK hynix and Sandisk will release at the Future of Memory and Storage 2026 exhibition in California this week / Courtesy of SK hynix SK hynix and Sandisk have introduced the industry's first standards for high-bandwidth flash (HBF), a storage technology designed to accelerate artificial intelligence (AI) inference by enabling faster data transfers, similar to the role high-bandwidth memory (HBM) plays in AI systems. According to SK hynix, the two companies will unveil the standards at the Future of Memory and Storage 2026 exhibition, held in California from Tuesday through Thursday (local time). Through keynote speeches and panel discussions, they will present HBF as a key technology for addressing memory bottlenecks in the AI era. In AI accelerators, HBF is designed to sit between HBM and storage devices such as solid-state drives (SSDs). It offers significantly higher bandwidth than SSDs while retaining the large storage capacity of NAND flash memory. As AI inference drives explosive growth in the amount of data processing, HBF is drawing attention as a technology capable of delivering both high bandwidth and scalable storage capacity. The new standards came six months after SK hynix formed a consortium with Sandisk. They defined two configurations of stacking eight or 16 NAND dies, supporting capacities of up to 512 gigabytes (GB). The standards also classified bandwidth into three grades, ranging from about 0.4 terabytes per second (Tbps) to 3.0 Tbps. SK hynix stressed that HBF and logic processors will be connected through Universal Chiplet Interconnect Express (UCIe), an open standard for high-speed chiplet interconnects, allowing HBF to be more flexibly integrated with central processing units (CPUs), graphics processing units (GPUs) and other logic processors. The standards also cover interface and electrical specifications, reliability and packaging guidelines for HBF die stacks, and software guidelines for data input and output. In the semiconductor industry, publishing technical standards is generally seen as a first step toward building an ecosystem around a new technology, allowing multiple companies to develop compatible products under a common specification. SK hynix said it will leverage the standard publication as an opportunity to expand the adoption of HBF technology in the AI storage market and foster the surrounding ecosystem. With Google and Tenstorrent currently participating in the HBF consortium, the consortium will expand its reach while enhancing technical maturity and market acceptance based on open collaboration. On the first day of the event, SK hynix Executive Vice President Kim Chun-sung and Vice President Kang Uk-song will deliver a joint keynote address on improving AI infrastructure efficiency through tiered memory architecture. On Thursday, SK hynix Vice President Lim Eui-cheol, Sandisk Vice President Rajeev Nagabhirava and Google DeepMind Senior Staff Engineer Xiaoyu Ma will join a panel discussion titled "Breaking the Memory Wall with HBF." Throughout the event, SK hynix will operate a booth to showcase its new technologies including its 10th-generation 375-layer 4D NAND wafer and products. "With the rapid spread of AI applications, we are at a point where overall data processing structures must be redesigned," Kim said. "Through HBF, SK hynix will expand the boundaries between memory and storage and contribute to building new architectures that enhance overall system efficiency."

Sandisk, SK hynix release flash memory spec for AI systems By Investing.com

MILPITAS, Calif. - Sandisk Corporation (NASDAQ:SNDK) and SK hynix Inc. announced today the release of a High Bandwidth Flash technical specification through the Open Compute Project, according to a press release statement. The specification was developed through the HBF technology workstream under OCP, with Sandisk and SK hynix as primary contributors. Google and Tenstorrent joined as consortium members during the standardization process. The work began in February. The specification provides a technical framework for companies and developers designing AI inference systems and accelerators. It defines system interface, electrical and technical guidelines for designing systems that use HBF technology, including performance expectations, the xPU-HBF host interface, reliability and packaging guidance for an HBF die stack, and a software user guide for read and write operations. "AI inference is creating a new set of memory requirements, and HBF technology is designed to meet that moment," said Alper Ilkbahar, Chief Technology Officer at Sandisk. "This specification helps give system designers a practical path to bring high-capacity, high-bandwidth memory closer to compute, while enabling more flexible architectures." The specification was released within the Open Compute Project framework, making the information openly available to the industry. The standard allows HBF technology to coexist with High Bandwidth Memory in AI compute systems. Sandisk will present a keynote at The Future of Memory and Storage Conference on Wednesday at 11:40 a.m. PT at the Santa Clara Convention Center. On Thursday at 9:45 a.m. PT, Sandisk, SK hynix and Google will participate in a panel discussion about HBF technology at the same conference. This article was generated with the support of AI and reviewed by an editor. For more information see our T&C.

Sandisk Corporation and Sk Hynix Release Hbf Technical Specification Through Open Compute Project

Sandisk Corporation and SK hynix Inc. announced the release of the HBF (High Bandwidth Flash) technical specification through the Open Compute Project (OCP), advancing the workstream to drive HBF standardization for the AI inference era, just six months after the consortium began work in February. The specification was developed through the HBF technology workstream under OCP, with Sandisk and SK hynix serving as primary contributors. Google and Tenstorrent joined as consortium members during this standardization process, contributing significantly to technology validation and the establishment of the standard. The specification provides companies and developers designing AI inference systems and accelerators with a common technical framework for incorporating HBF technology where larger, near-compute memory capacity and higher bandwidth are needed to improve power and performance metrics and help reduce total cost of ownership. Modern AI inference systems need high-bandwidth memory positioned close to compute cores, while the demand for greater near-compute memory capacity continues to grow with the requirements of large language models and emerging AI workloads. HBF technology is designed to address this need by combining high bandwidth with high capacity, helping data center system designers improve interactivity and throughput during model serving. The specification defines system interface, electrical and other technical guidelines for designing systems that interact with and use HBF technology, including basic performance expectations, the xPU-HBF host interface, reliability and packaging guidance for an HBF die stack, and a software user guide for read and write operations. As one of the first technical standards of its kind in the memory and storage industry, the specification helps give AI compute system designers added flexibility to build systems where HBF technology can coexist with High Bandwidth Memory, helping support ecosystem readiness. The specification was released within the Open Compute Project framework, meaning the information is openly available to the industry. Sandisk and SK hynix proactively published the specification to position HBF technology as the de facto standard in the rapidly evolving AI storage market. Their strategy involves fostering an early-stage ecosystem, increasing the visibility of HBF technology?s adoption for customers, and accelerating market expansion and technological maturity through open collaboration and membership in the consortium.