AI agent designs complete RISC-V CPU from scratch in 12 hours using autonomous workflow

AI Agent Designs CPU in Record Time

Chip design startup Verkor.io has achieved what it claims is a first in AI chip design: an autonomous agent that built a working RISC-V CPU from specification to GDSII layout file in just 12 hours 1

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. The agentic AI system, called Design Conductor, took a 219-word requirements document and generated a verified, layout-ready design—a process that typically requires 18 to 36 months with engineering teams numbering in the hundreds 1

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. This marks the first time an AI agent designs CPU hardware through the complete conventional design cycle—design, build, test, and refine—entirely on its own rather than relying on separate automation tools for each stage 2

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The resulting processor, dubbed VerCore, features a five-stage pipeline design with instruction fetch, decode, execute, memory, and writeback stages, incorporating early branch resolution and operand forwarding 1

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. The in-order, single-issue core achieved timing at 1.48 GHz on the ASAP7 7nm process design kit and scored 3,261 on the CoreMark benchmark—performance comparable to Intel's Celeron SU2300, a 2011 mobile chip based on the Penryn architecture 1

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How Design Conductor Works

Design Conductor is not itself an AI model but a harness tool that constrains large language models to follow specific instructions in pursuit of a defined objective 2

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. During optimization, the system independently implemented a fast Booth-Wallace multiplier that clocked at 2.57 GHz and selected a one-cycle branch penalty design after implementing and testing both one-cycle and two-cycle variants 1

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. The autonomous hardware design process required "many tens of billions of tokens" even for this comparatively simple design 1

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Verkor.io's research paper candidly acknowledges limitations in the underlying language models. The agent sometimes "underestimates the complexity of work that is required to address certain issues," such as attempting to deepen the pipeline architecture instead of seeking simpler explanations when failing to meet timing 1

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. Researchers also observed the model reasoning about Verilog, an event-driven language, as if it were sequential code, which complicated debugging timing issues though it didn't impact functional correctness 1

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Practical Limitations and Future Outlook

A critical caveat remains: VerCore has not been physically fabricated and was instead verified in simulation using Spike, a reference RISC-V ISA simulator 1

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. ASAP7 is an academic process design kit developed by Arizona State University in collaboration with ARM Research, not a production 7nm node 2

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. Verkor says the design can run a uCLinux variant in simulation 1

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The researchers estimate that five to 10 human experts will still be required to guide the system toward a production-ready chip 1

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. Additionally, compute requirements grow non-linearly as design complexity increases, which makes the process less practical on a commercial scale for leading-edge chips that cost north of $400 million 1

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. Verkor.io plans to release VerCore's RTL source and build scripts by the end of April and showcase an FPGA implementation at the Design Automation Conference (DAC) in Long Beach, California, in July 1

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. This transparency will allow hardware designers and third-party engineers to verify the company's claims and assess whether AI-driven Electronic Design Automation (EDA) workflows can scale beyond academic demonstrations to address real-world production challenges.